stmmac: extend CSR Clock Range programming

[mirror_ubuntu-artful-kernel.git] / include / linux / stmmac.h

diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 4aef9baff12bd887f226640a7d0dd34e4ce1d3bb..cf64031863596d37440cfeba6995ec878895ef6d 100644 (file)
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -37,28 +37,29 @@
  * This could also be configured at run time using CPU freq framework. */
 
 /* MDC Clock Selection define*/
-#define        STMMAC_CSR_60_100M      0       /* MDC = clk_scr_i/42 */
-#define        STMMAC_CSR_100_150M     1       /* MDC = clk_scr_i/62 */
-#define        STMMAC_CSR_20_35M       2       /* MDC = clk_scr_i/16 */
-#define        STMMAC_CSR_35_60M       3       /* MDC = clk_scr_i/26 */
-#define        STMMAC_CSR_150_250M     4       /* MDC = clk_scr_i/102 */
-#define        STMMAC_CSR_250_300M     5       /* MDC = clk_scr_i/122 */
-
-/* FIXME: The MDC clock could be set higher than the IEEE 802.3
+#define        STMMAC_CSR_60_100M      0x0     /* MDC = clk_scr_i/42 */
+#define        STMMAC_CSR_100_150M     0x1     /* MDC = clk_scr_i/62 */
+#define        STMMAC_CSR_20_35M       0x2     /* MDC = clk_scr_i/16 */
+#define        STMMAC_CSR_35_60M       0x3     /* MDC = clk_scr_i/26 */
+#define        STMMAC_CSR_150_250M     0x4     /* MDC = clk_scr_i/102 */
+#define        STMMAC_CSR_250_300M     0x5     /* MDC = clk_scr_i/122 */
+
+/* The MDC clock could be set higher than the IEEE 802.3
  * specified frequency limit 0f 2.5 MHz, by programming a clock divider
  * of value different than the above defined values. The resultant MDIO
  * clock frequency of 12.5 MHz is applicable for the interfacing chips
  * supporting higher MDC clocks.
  * The MDC clock selection macros need to be defined for MDC clock rate
  * of 12.5 MHz, corresponding to the following selection.
- * 1000 clk_csr_i/4
- * 1001 clk_csr_i/6
- * 1010 clk_csr_i/8
- * 1011 clk_csr_i/10
- * 1100 clk_csr_i/12
- * 1101 clk_csr_i/14
- * 1110 clk_csr_i/16
- * 1111 clk_csr_i/18 */
+ */
+#define STMMAC_CSR_I_4         0x8     /* clk_csr_i/4 */
+#define STMMAC_CSR_I_6         0x9     /* clk_csr_i/6 */
+#define STMMAC_CSR_I_8         0xA     /* clk_csr_i/8 */
+#define STMMAC_CSR_I_10                0xB     /* clk_csr_i/10 */
+#define STMMAC_CSR_I_12                0xC     /* clk_csr_i/12 */
+#define STMMAC_CSR_I_14                0xD     /* clk_csr_i/14 */
+#define STMMAC_CSR_I_16                0xE     /* clk_csr_i/16 */
+#define STMMAC_CSR_I_18                0xF     /* clk_csr_i/18 */
 
 /* AXI DMA Burst length suported */
 #define DMA_AXI_BLEN_4         (1 << 1)