Merge tag 'pull-target-arm-20240111' of https://git.linaro.org/people/pmaydell/qemu...

[mirror_qemu.git] / include / standard-headers / linux / pci_regs.h

diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
index 85ab1278811e1495d1ee007dfcb0ef860a779d4c..a39193213ff25ba24233fe28bc4977f38c294702 100644 (file)
--- a/include/standard-headers/linux/pci_regs.h
+++ b/include/standard-headers/linux/pci_regs.h
@@ -80,6 +80,7 @@
 #define  PCI_HEADER_TYPE_NORMAL                0
 #define  PCI_HEADER_TYPE_BRIDGE                1
 #define  PCI_HEADER_TYPE_CARDBUS       2
+#define  PCI_HEADER_TYPE_MFD           0x80    /* Multi-Function Device (possible) */
 
 #define PCI_BIST               0x0f    /* 8 bits */
 #define  PCI_BIST_CODE_MASK    0x0f    /* Return result */
@@ -637,6 +638,7 @@
 #define PCI_EXP_RTCAP          0x1e    /* Root Capabilities */
 #define  PCI_EXP_RTCAP_CRSVIS  0x0001  /* CRS Software Visibility capability */
 #define PCI_EXP_RTSTA          0x20    /* Root Status */
+#define  PCI_EXP_RTSTA_PME_RQ_ID 0x0000ffff /* PME Requester ID */
 #define  PCI_EXP_RTSTA_PME     0x00010000 /* PME status */
 #define  PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
 /*
@@ -693,6 +695,7 @@
 #define  PCI_EXP_LNKCTL2_TX_MARGIN     0x0380 /* Transmit Margin */
 #define  PCI_EXP_LNKCTL2_HASD          0x0020 /* HW Autonomous Speed Disable */
 #define PCI_EXP_LNKSTA2                0x32    /* Link Status 2 */
+#define  PCI_EXP_LNKSTA2_FLIT          0x0400 /* Flit Mode Status */
 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32    /* end of v2 EPs w/ link */
 #define PCI_EXP_SLTCAP2                0x34    /* Slot Capabilities 2 */
 #define  PCI_EXP_SLTCAP2_IBPD  0x00000001 /* In-band PD Disable Supported */
@@ -737,6 +740,7 @@
 #define PCI_EXT_CAP_ID_DVSEC   0x23    /* Designated Vendor-Specific */
 #define PCI_EXT_CAP_ID_DLF     0x25    /* Data Link Feature */
 #define PCI_EXT_CAP_ID_PL_16GT 0x26    /* Physical Layer 16.0 GT/s */
+#define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
 #define PCI_EXT_CAP_ID_DOE     0x2E    /* Data Object Exchange */
 #define PCI_EXT_CAP_ID_MAX     PCI_EXT_CAP_ID_DOE
 
@@ -928,12 +932,13 @@
 
 /* Process Address Space ID */
 #define PCI_PASID_CAP          0x04    /* PASID feature register */
-#define  PCI_PASID_CAP_EXEC    0x02    /* Exec permissions Supported */
-#define  PCI_PASID_CAP_PRIV    0x04    /* Privilege Mode Supported */
+#define  PCI_PASID_CAP_EXEC    0x0002  /* Exec permissions Supported */
+#define  PCI_PASID_CAP_PRIV    0x0004  /* Privilege Mode Supported */
+#define  PCI_PASID_CAP_WIDTH   0x1f00
 #define PCI_PASID_CTRL         0x06    /* PASID control register */
-#define  PCI_PASID_CTRL_ENABLE 0x01    /* Enable bit */
-#define  PCI_PASID_CTRL_EXEC   0x02    /* Exec permissions Enable */
-#define  PCI_PASID_CTRL_PRIV   0x04    /* Privilege Mode Enable */
+#define  PCI_PASID_CTRL_ENABLE 0x0001  /* Enable bit */
+#define  PCI_PASID_CTRL_EXEC   0x0002  /* Exec permissions Enable */
+#define  PCI_PASID_CTRL_PRIV   0x0004  /* Privilege Mode Enable */
 #define PCI_EXT_CAP_PASID_SIZEOF       8
 
 /* Single Root I/O Virtualization */
@@ -973,6 +978,8 @@
 #define  PCI_LTR_VALUE_MASK    0x000003ff
 #define  PCI_LTR_SCALE_MASK    0x00001c00
 #define  PCI_LTR_SCALE_SHIFT   10
+#define  PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */
+#define  PCI_LTR_NOSNOOP_SCALE 0x1c000000 /* Scale for Max Value */
 #define PCI_EXT_CAP_LTR_SIZEOF 8
 
 /* Access Control Service */
@@ -1040,9 +1047,16 @@
 #define PCI_EXP_DPC_STATUS             0x08    /* DPC Status */
 #define  PCI_EXP_DPC_STATUS_TRIGGER        0x0001 /* Trigger Status */
 #define  PCI_EXP_DPC_STATUS_TRIGGER_RSN            0x0006 /* Trigger Reason */
+#define  PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR  0x0000 /* Uncorrectable error */
+#define  PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE    0x0002 /* Rcvd ERR_NONFATAL */
+#define  PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE     0x0004 /* Rcvd ERR_FATAL */
+#define  PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT 0x0006 /* Reason in Trig Reason Extension field */
 #define  PCI_EXP_DPC_STATUS_INTERRUPT      0x0008 /* Interrupt Status */
 #define  PCI_EXP_DPC_RP_BUSY               0x0010 /* Root Port Busy */
 #define  PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */
+#define  PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO         0x0000  /* RP PIO error */
+#define  PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER     0x0020  /* DPC SW Trigger bit */
+#define  PCI_EXP_DPC_RP_PIO_FEP                    0x1f00 /* RP PIO First Err Ptr */
 
 #define PCI_EXP_DPC_SOURCE_ID           0x0A   /* DPC Source Identifier */
 
@@ -1086,6 +1100,8 @@
 #define  PCI_L1SS_CTL1_LTR_L12_TH_VALUE        0x03ff0000  /* LTR_L1.2_THRESHOLD_Value */
 #define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE        0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */
 #define PCI_L1SS_CTL2          0x0c    /* Control 2 Register */
+#define  PCI_L1SS_CTL2_T_PWR_ON_SCALE  0x00000003  /* T_POWER_ON Scale */
+#define  PCI_L1SS_CTL2_T_PWR_ON_VALUE  0x000000f8  /* T_POWER_ON Value */
 
 /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
 #define PCI_DVSEC_HEADER1              0x4 /* Designated Vendor-Specific Header1 */