drm/amdgpu: optionally do a writeback but don't invalidate TC for IB fences

[mirror_ubuntu-jammy-kernel.git] / include / uapi / drm / amdgpu_drm.h

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 4d21191aaed0f92aeb5cfd3e345b9befa8e549f8..78fe828f2f79cb4f864181739ee79463197e2963 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -78,6 +78,12 @@ extern "C" {
 #define AMDGPU_GEM_DOMAIN_GDS          0x8
 #define AMDGPU_GEM_DOMAIN_GWS          0x10
 #define AMDGPU_GEM_DOMAIN_OA           0x20
+#define AMDGPU_GEM_DOMAIN_MASK         (AMDGPU_GEM_DOMAIN_CPU | \
+                                        AMDGPU_GEM_DOMAIN_GTT | \
+                                        AMDGPU_GEM_DOMAIN_VRAM | \
+                                        AMDGPU_GEM_DOMAIN_GDS | \
+                                        AMDGPU_GEM_DOMAIN_GWS | \
+                                        AMDGPU_GEM_DOMAIN_OA)
 
 /* Flag that CPU access will be required for the case of VRAM domain */
 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED  (1 << 0)
@@ -520,6 +526,10 @@ union drm_amdgpu_cs {
 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
 
+/* The IB fence should do the L2 writeback but not invalidate any shader
+ * caches (L2/vL1/sL1/I$). */
+#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
+
 struct drm_amdgpu_cs_chunk_ib {
        __u32 _pad;
        /** AMDGPU_IB_FLAG_* */
@@ -618,6 +628,8 @@ struct drm_amdgpu_cs_chunk_data {
        #define AMDGPU_INFO_FW_SOS              0x0c
        /* Subquery id: Query PSP ASD firmware version */
        #define AMDGPU_INFO_FW_ASD              0x0d
+       /* Subquery id: Query VCN firmware version */
+       #define AMDGPU_INFO_FW_VCN              0x0e
 /* number of bytes moved for TTM migration */
 #define AMDGPU_INFO_NUM_BYTES_MOVED            0x0f
 /* the used VRAM size */
@@ -664,6 +676,10 @@ struct drm_amdgpu_cs_chunk_data {
        #define AMDGPU_INFO_SENSOR_VDDNB                0x6
        /* Subquery id: Query graphics voltage */
        #define AMDGPU_INFO_SENSOR_VDDGFX               0x7
+       /* Subquery id: Query GPU stable pstate shader clock */
+       #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK               0x8
+       /* Subquery id: Query GPU stable pstate memory clock */
+       #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK               0x9
 /* Number of VRAM page faults on CPU access. */
 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS   0x1E
 #define AMDGPU_INFO_VRAM_LOST_COUNTER          0x1F
@@ -802,6 +818,7 @@ struct drm_amdgpu_info_firmware {
 #define AMDGPU_VRAM_TYPE_GDDR5 5
 #define AMDGPU_VRAM_TYPE_HBM   6
 #define AMDGPU_VRAM_TYPE_DDR3  7
+#define AMDGPU_VRAM_TYPE_DDR4  8
 
 struct drm_amdgpu_info_device {
        /** PCI Device ID */