*/
#include "qemu/osdep.h"
-#include "qemu-common.h"
#include "qemu.h"
#include "user-internals.h"
#include "elf.h"
put_user_u16(__x, (gaddr)); \
})
-/* Commpage handling -- there is no commpage for AArch64 */
+/*
+ * Similar to code in accel/tcg/user-exec.c, but outside the execution loop.
+ * Must be called with mmap_lock.
+ * We get the PC of the entry address - which is as good as anything,
+ * on a real kernel what you get depends on which mode it uses.
+ */
+static void *atomic_mmu_lookup(CPUArchState *env, uint32_t addr, int size)
+{
+ int need_flags = PAGE_READ | PAGE_WRITE_ORG | PAGE_VALID;
+ int page_flags;
+
+ /* Enforce guest required alignment. */
+ if (unlikely(addr & (size - 1))) {
+ force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr);
+ return NULL;
+ }
+
+ page_flags = page_get_flags(addr);
+ if (unlikely((page_flags & need_flags) != need_flags)) {
+ force_sig_fault(TARGET_SIGSEGV,
+ page_flags & PAGE_VALID ?
+ TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr);
+ return NULL;
+ }
+
+ return g2h(env_cpu(env), addr);
+}
+
+/*
+ * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst
+ * Input:
+ * r0 = oldval
+ * r1 = newval
+ * r2 = pointer to target value
+ *
+ * Output:
+ * r0 = 0 if *ptr was changed, non-0 if no exchange happened
+ * C set if *ptr was changed, clear if no exchange happened
+ */
+static void arm_kernel_cmpxchg32_helper(CPUARMState *env)
+{
+ uint32_t oldval, newval, val, addr, cpsr, *host_addr;
+
+ oldval = env->regs[0];
+ newval = env->regs[1];
+ addr = env->regs[2];
+
+ mmap_lock();
+ host_addr = atomic_mmu_lookup(env, addr, 4);
+ if (!host_addr) {
+ mmap_unlock();
+ return;
+ }
+
+ val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval);
+ mmap_unlock();
+
+ cpsr = (val == oldval) * CPSR_C;
+ cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
+ env->regs[0] = cpsr ? 0 : -1;
+}
/*
- * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
+ * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst
* Input:
* r0 = pointer to oldval
* r1 = pointer to newval
{
uint64_t oldval, newval, val;
uint32_t addr, cpsr;
+ uint64_t *host_addr;
- /* Based on the 32 bit code in do_kernel_trap */
-
- /* XXX: This only works between threads, not between processes.
- It's probably possible to implement this with native host
- operations. However things like ldrex/strex are much harder so
- there's not much point trying. */
- start_exclusive();
- cpsr = cpsr_read(env);
- addr = env->regs[2];
-
- if (get_user_u64(oldval, env->regs[0])) {
- env->exception.vaddress = env->regs[0];
+ addr = env->regs[0];
+ if (get_user_u64(oldval, addr)) {
goto segv;
- };
+ }
- if (get_user_u64(newval, env->regs[1])) {
- env->exception.vaddress = env->regs[1];
+ addr = env->regs[1];
+ if (get_user_u64(newval, addr)) {
goto segv;
- };
+ }
- if (get_user_u64(val, addr)) {
- env->exception.vaddress = addr;
- goto segv;
+ mmap_lock();
+ addr = env->regs[2];
+ host_addr = atomic_mmu_lookup(env, addr, 8);
+ if (!host_addr) {
+ mmap_unlock();
+ return;
}
+#ifdef CONFIG_ATOMIC64
+ val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval);
+ cpsr = (val == oldval) * CPSR_C;
+#else
+ /*
+ * This only works between threads, not between processes, but since
+ * the host has no 64-bit cmpxchg, it is the best that we can do.
+ */
+ start_exclusive();
+ val = *host_addr;
if (val == oldval) {
- val = newval;
-
- if (put_user_u64(val, addr)) {
- env->exception.vaddress = addr;
- goto segv;
- };
-
- env->regs[0] = 0;
- cpsr |= CPSR_C;
+ *host_addr = newval;
+ cpsr = CPSR_C;
} else {
- env->regs[0] = -1;
- cpsr &= ~CPSR_C;
+ cpsr = 0;
}
- cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
end_exclusive();
+#endif
+ mmap_unlock();
+
+ cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
+ env->regs[0] = cpsr ? 0 : -1;
return;
-segv:
- end_exclusive();
- /* We get the PC of the entry address - which is as good as anything,
- on a real kernel what you get depends on which mode it uses. */
- /* XXX: check env->error_code */
- force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR,
- env->exception.vaddress);
+ segv:
+ force_sig_fault(TARGET_SIGSEGV,
+ page_get_flags(addr) & PAGE_VALID ?
+ TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr);
}
/* Handle a jump to the kernel code page. */
do_kernel_trap(CPUARMState *env)
{
uint32_t addr;
- uint32_t cpsr;
- uint32_t val;
switch (env->regs[15]) {
case 0xffff0fa0: /* __kernel_memory_barrier */
- /* ??? No-op. Will need to do better for SMP. */
+ smp_mb();
break;
case 0xffff0fc0: /* __kernel_cmpxchg */
- /* XXX: This only works between threads, not between processes.
- It's probably possible to implement this with native host
- operations. However things like ldrex/strex are much harder so
- there's not much point trying. */
- start_exclusive();
- cpsr = cpsr_read(env);
- addr = env->regs[2];
- /* FIXME: This should SEGV if the access fails. */
- if (get_user_u32(val, addr))
- val = ~env->regs[0];
- if (val == env->regs[0]) {
- val = env->regs[1];
- /* FIXME: Check for segfaults. */
- put_user_u32(val, addr);
- env->regs[0] = 0;
- cpsr |= CPSR_C;
- } else {
- env->regs[0] = -1;
- cpsr &= ~CPSR_C;
- }
- cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
- end_exclusive();
+ arm_kernel_cmpxchg32_helper(env);
break;
case 0xffff0fe0: /* __kernel_get_tls */
env->regs[0] = cpu_get_tls(env);
/* Jump back to the caller. */
addr = env->regs[14];
if (addr & 1) {
- env->thumb = 1;
+ env->thumb = true;
addr &= ~1;
}
env->regs[15] = addr;
}
break;
case EXCP_SEMIHOST:
- env->regs[0] = do_common_semihosting(cs);
+ do_common_semihosting(cs);
env->regs[15] += env->thumb ? 2 : 4;
break;
case EXCP_INTERRUPT:
for(i = 0; i < 16; i++) {
env->regs[i] = regs->uregs[i];
}
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
/* Enable BE8. */
if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
&& (info->elf_flags & EF_ARM_BE8)) {
projects / mirror_qemu.git / blobdiff