#include <time.h>
#include "qemu.h"
-#include "disas.h"
+#include "disas/disas.h"
#ifdef _ARCH_PPC64
#undef ARCH_DLINFO
#undef ELF_PLATFORM
#undef ELF_HWCAP
+#undef ELF_HWCAP2
#undef ELF_CLASS
#undef ELF_DATA
#undef ELF_ARCH
#define ELF_DATA ELFDATA2LSB
#endif
-typedef target_ulong target_elf_greg_t;
+#ifdef TARGET_ABI_MIPSN32
+typedef abi_ullong target_elf_greg_t;
+#define tswapreg(ptr) tswap64(ptr)
+#else
+typedef abi_ulong target_elf_greg_t;
+#define tswapreg(ptr) tswapal(ptr)
+#endif
+
#ifdef USE_UID16
-typedef target_ushort target_uid_t;
-typedef target_ushort target_gid_t;
+typedef abi_ushort target_uid_t;
+typedef abi_ushort target_gid_t;
#else
-typedef target_uint target_uid_t;
-typedef target_uint target_gid_t;
+typedef abi_uint target_uid_t;
+typedef abi_uint target_gid_t;
#endif
-typedef target_int target_pid_t;
+typedef abi_int target_pid_t;
#ifdef TARGET_I386
static const char *get_elf_platform(void)
{
static char elf_platform[] = "i386";
- int family = (thread_env->cpuid_version >> 8) & 0xff;
+ int family = object_property_get_int(OBJECT(thread_cpu), "family", NULL);
if (family > 6)
family = 6;
if (family >= 3)
static uint32_t get_elf_hwcap(void)
{
- return thread_env->cpuid_features;
+ X86CPU *cpu = X86_CPU(thread_cpu);
+
+ return cpu->env.features[FEAT_1_EDX];
}
#ifdef TARGET_X86_64
#ifdef TARGET_ARM
+#ifndef TARGET_AARCH64
+/* 32 bit ARM definitions */
+
#define ELF_START_MMAP 0x80000000
-#define elf_check_arch(x) ( (x) == EM_ARM )
+#define elf_check_arch(x) ((x) == ELF_MACHINE)
+#define ELF_ARCH ELF_MACHINE
#define ELF_CLASS ELFCLASS32
-#define ELF_ARCH EM_ARM
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
abi_long stack = infop->start_stack;
memset(regs, 0, sizeof(*regs));
+
regs->ARM_cpsr = 0x10;
if (infop->entry & 1)
regs->ARM_cpsr |= CPSR_T;
static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUARMState *env)
{
- (*regs)[0] = tswapl(env->regs[0]);
- (*regs)[1] = tswapl(env->regs[1]);
- (*regs)[2] = tswapl(env->regs[2]);
- (*regs)[3] = tswapl(env->regs[3]);
- (*regs)[4] = tswapl(env->regs[4]);
- (*regs)[5] = tswapl(env->regs[5]);
- (*regs)[6] = tswapl(env->regs[6]);
- (*regs)[7] = tswapl(env->regs[7]);
- (*regs)[8] = tswapl(env->regs[8]);
- (*regs)[9] = tswapl(env->regs[9]);
- (*regs)[10] = tswapl(env->regs[10]);
- (*regs)[11] = tswapl(env->regs[11]);
- (*regs)[12] = tswapl(env->regs[12]);
- (*regs)[13] = tswapl(env->regs[13]);
- (*regs)[14] = tswapl(env->regs[14]);
- (*regs)[15] = tswapl(env->regs[15]);
-
- (*regs)[16] = tswapl(cpsr_read((CPUARMState *)env));
- (*regs)[17] = tswapl(env->regs[0]); /* XXX */
+ (*regs)[0] = tswapreg(env->regs[0]);
+ (*regs)[1] = tswapreg(env->regs[1]);
+ (*regs)[2] = tswapreg(env->regs[2]);
+ (*regs)[3] = tswapreg(env->regs[3]);
+ (*regs)[4] = tswapreg(env->regs[4]);
+ (*regs)[5] = tswapreg(env->regs[5]);
+ (*regs)[6] = tswapreg(env->regs[6]);
+ (*regs)[7] = tswapreg(env->regs[7]);
+ (*regs)[8] = tswapreg(env->regs[8]);
+ (*regs)[9] = tswapreg(env->regs[9]);
+ (*regs)[10] = tswapreg(env->regs[10]);
+ (*regs)[11] = tswapreg(env->regs[11]);
+ (*regs)[12] = tswapreg(env->regs[12]);
+ (*regs)[13] = tswapreg(env->regs[13]);
+ (*regs)[14] = tswapreg(env->regs[14]);
+ (*regs)[15] = tswapreg(env->regs[15]);
+
+ (*regs)[16] = tswapreg(cpsr_read((CPUARMState *)env));
+ (*regs)[17] = tswapreg(env->regs[0]); /* XXX */
}
#define USE_ELF_CORE_DUMP
ARM_HWCAP_ARM_EDSP = 1 << 7,
ARM_HWCAP_ARM_JAVA = 1 << 8,
ARM_HWCAP_ARM_IWMMXT = 1 << 9,
- ARM_HWCAP_ARM_THUMBEE = 1 << 10,
- ARM_HWCAP_ARM_NEON = 1 << 11,
- ARM_HWCAP_ARM_VFPv3 = 1 << 12,
- ARM_HWCAP_ARM_VFPv3D16 = 1 << 13,
+ ARM_HWCAP_ARM_CRUNCH = 1 << 10,
+ ARM_HWCAP_ARM_THUMBEE = 1 << 11,
+ ARM_HWCAP_ARM_NEON = 1 << 12,
+ ARM_HWCAP_ARM_VFPv3 = 1 << 13,
+ ARM_HWCAP_ARM_VFPv3D16 = 1 << 14,
+ ARM_HWCAP_ARM_TLS = 1 << 15,
+ ARM_HWCAP_ARM_VFPv4 = 1 << 16,
+ ARM_HWCAP_ARM_IDIVA = 1 << 17,
+ ARM_HWCAP_ARM_IDIVT = 1 << 18,
+ ARM_HWCAP_ARM_VFPD32 = 1 << 19,
+ ARM_HWCAP_ARM_LPAE = 1 << 20,
+ ARM_HWCAP_ARM_EVTSTRM = 1 << 21,
};
+enum {
+ ARM_HWCAP2_ARM_AES = 1 << 0,
+ ARM_HWCAP2_ARM_PMULL = 1 << 1,
+ ARM_HWCAP2_ARM_SHA1 = 1 << 2,
+ ARM_HWCAP2_ARM_SHA2 = 1 << 3,
+ ARM_HWCAP2_ARM_CRC32 = 1 << 4,
+};
+
+/* The commpage only exists for 32 bit kernels */
+
#define TARGET_HAS_VALIDATE_GUEST_SPACE
/* Return 1 if the proposed guest space is suitable for the guest.
* Return 0 if the proposed guest space isn't suitable, but another
return 1; /* All good */
}
-
#define ELF_HWCAP get_elf_hwcap()
+#define ELF_HWCAP2 get_elf_hwcap2()
static uint32_t get_elf_hwcap(void)
{
- CPUARMState *e = thread_env;
+ ARMCPU *cpu = ARM_CPU(thread_cpu);
uint32_t hwcaps = 0;
hwcaps |= ARM_HWCAP_ARM_SWP;
hwcaps |= ARM_HWCAP_ARM_HALF;
hwcaps |= ARM_HWCAP_ARM_THUMB;
hwcaps |= ARM_HWCAP_ARM_FAST_MULT;
- hwcaps |= ARM_HWCAP_ARM_FPA;
/* probe for the extra features */
#define GET_FEATURE(feat, hwcap) \
- do {if (arm_feature(e, feat)) { hwcaps |= hwcap; } } while (0)
+ do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
+ /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */
+ GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP);
GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3);
- GET_FEATURE(ARM_FEATURE_VFP_FP16, ARM_HWCAP_ARM_VFPv3D16);
+ GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
+ GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4);
+ GET_FEATURE(ARM_FEATURE_ARM_DIV, ARM_HWCAP_ARM_IDIVA);
+ GET_FEATURE(ARM_FEATURE_THUMB_DIV, ARM_HWCAP_ARM_IDIVT);
+ /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c.
+ * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of
+ * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated
+ * to our VFP_FP16 feature bit.
+ */
+ GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32);
+ GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
+
+ return hwcaps;
+}
+
+static uint32_t get_elf_hwcap2(void)
+{
+ ARMCPU *cpu = ARM_CPU(thread_cpu);
+ uint32_t hwcaps = 0;
+
+ GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP2_ARM_AES);
+ GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP2_ARM_PMULL);
+ GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP2_ARM_SHA1);
+ GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP2_ARM_SHA2);
+ GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP2_ARM_CRC32);
+ return hwcaps;
+}
+
+#undef GET_FEATURE
+
+#else
+/* 64 bit ARM definitions */
+#define ELF_START_MMAP 0x80000000
+
+#define elf_check_arch(x) ((x) == ELF_MACHINE)
+
+#define ELF_ARCH ELF_MACHINE
+#define ELF_CLASS ELFCLASS64
+#define ELF_PLATFORM "aarch64"
+
+static inline void init_thread(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+ abi_long stack = infop->start_stack;
+ memset(regs, 0, sizeof(*regs));
+
+ regs->pc = infop->entry & ~0x3ULL;
+ regs->sp = stack;
+}
+
+#define ELF_NREG 34
+typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
+
+static void elf_core_copy_regs(target_elf_gregset_t *regs,
+ const CPUARMState *env)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ (*regs)[i] = tswapreg(env->xregs[i]);
+ }
+ (*regs)[32] = tswapreg(env->pc);
+ (*regs)[33] = tswapreg(pstate_read((CPUARMState *)env));
+}
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE 4096
+
+enum {
+ ARM_HWCAP_A64_FP = 1 << 0,
+ ARM_HWCAP_A64_ASIMD = 1 << 1,
+ ARM_HWCAP_A64_EVTSTRM = 1 << 2,
+ ARM_HWCAP_A64_AES = 1 << 3,
+ ARM_HWCAP_A64_PMULL = 1 << 4,
+ ARM_HWCAP_A64_SHA1 = 1 << 5,
+ ARM_HWCAP_A64_SHA2 = 1 << 6,
+ ARM_HWCAP_A64_CRC32 = 1 << 7,
+};
+
+#define ELF_HWCAP get_elf_hwcap()
+
+static uint32_t get_elf_hwcap(void)
+{
+ ARMCPU *cpu = ARM_CPU(thread_cpu);
+ uint32_t hwcaps = 0;
+
+ hwcaps |= ARM_HWCAP_A64_FP;
+ hwcaps |= ARM_HWCAP_A64_ASIMD;
+
+ /* probe for the extra features */
+#define GET_FEATURE(feat, hwcap) \
+ do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
+ GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP_A64_AES);
+ GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP_A64_PMULL);
+ GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1);
+ GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2);
+ GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32);
#undef GET_FEATURE
return hwcaps;
}
-#endif
+#endif /* not TARGET_AARCH64 */
+#endif /* TARGET_ARM */
#ifdef TARGET_UNICORE32
QEMU_PPC_FEATURE_TRUE_LE = 0x00000002,
QEMU_PPC_FEATURE_PPC_LE = 0x00000001,
+
+ /* Feature definitions in AT_HWCAP2. */
+ QEMU_PPC_FEATURE2_ARCH_2_07 = 0x80000000, /* ISA 2.07 */
+ QEMU_PPC_FEATURE2_HAS_HTM = 0x40000000, /* Hardware Transactional Memory */
+ QEMU_PPC_FEATURE2_HAS_DSCR = 0x20000000, /* Data Stream Control Register */
+ QEMU_PPC_FEATURE2_HAS_EBB = 0x10000000, /* Event Base Branching */
+ QEMU_PPC_FEATURE2_HAS_ISEL = 0x08000000, /* Integer Select */
+ QEMU_PPC_FEATURE2_HAS_TAR = 0x04000000, /* Target Address Register */
};
#define ELF_HWCAP get_elf_hwcap()
static uint32_t get_elf_hwcap(void)
{
- CPUPPCState *e = thread_env;
+ PowerPCCPU *cpu = POWERPC_CPU(thread_cpu);
uint32_t features = 0;
/* We don't have to be terribly complete here; the high points are
Altivec/FP/SPE support. Anything else is just a bonus. */
#define GET_FEATURE(flag, feature) \
- do {if (e->insns_flags & flag) features |= feature; } while(0)
+ do { if (cpu->env.insns_flags & flag) { features |= feature; } } while (0)
+#define GET_FEATURE2(flag, feature) \
+ do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0)
GET_FEATURE(PPC_64B, QEMU_PPC_FEATURE_64);
GET_FEATURE(PPC_FLOAT, QEMU_PPC_FEATURE_HAS_FPU);
GET_FEATURE(PPC_ALTIVEC, QEMU_PPC_FEATURE_HAS_ALTIVEC);
GET_FEATURE(PPC_SPE_DOUBLE, QEMU_PPC_FEATURE_HAS_EFP_DOUBLE);
GET_FEATURE(PPC_BOOKE, QEMU_PPC_FEATURE_BOOKE);
GET_FEATURE(PPC_405_MAC, QEMU_PPC_FEATURE_HAS_4xxMAC);
+ GET_FEATURE2(PPC2_DFP, QEMU_PPC_FEATURE_HAS_DFP);
+ GET_FEATURE2(PPC2_VSX, QEMU_PPC_FEATURE_HAS_VSX);
+ GET_FEATURE2((PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 |
+ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206),
+ QEMU_PPC_FEATURE_ARCH_2_06);
+#undef GET_FEATURE
+#undef GET_FEATURE2
+
+ return features;
+}
+
+#define ELF_HWCAP2 get_elf_hwcap2()
+
+static uint32_t get_elf_hwcap2(void)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(thread_cpu);
+ uint32_t features = 0;
+
+#define GET_FEATURE(flag, feature) \
+ do { if (cpu->env.insns_flags & flag) { features |= feature; } } while (0)
+#define GET_FEATURE2(flag, feature) \
+ do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0)
+
+ GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL);
+ GET_FEATURE2(PPC2_BCTAR_ISA207, QEMU_PPC_FEATURE2_HAS_TAR);
+ GET_FEATURE2((PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
+ PPC2_ISA207S), QEMU_PPC_FEATURE2_ARCH_2_07);
+
#undef GET_FEATURE
+#undef GET_FEATURE2
return features;
}
#define DLINFO_ARCH_ITEMS 5
#define ARCH_DLINFO \
do { \
- NEW_AUX_ENT(AT_DCACHEBSIZE, 0x20); \
- NEW_AUX_ENT(AT_ICACHEBSIZE, 0x20); \
+ PowerPCCPU *cpu = POWERPC_CPU(thread_cpu); \
+ NEW_AUX_ENT(AT_DCACHEBSIZE, cpu->env.dcache_line_size); \
+ NEW_AUX_ENT(AT_ICACHEBSIZE, cpu->env.icache_line_size); \
NEW_AUX_ENT(AT_UCACHEBSIZE, 0); \
/* \
* Now handle glibc compatibility. \
NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
} while (0)
+static inline uint32_t get_ppc64_abi(struct image_info *infop);
+
static inline void init_thread(struct target_pt_regs *_regs, struct image_info *infop)
{
_regs->gpr[1] = infop->start_stack;
#if defined(TARGET_PPC64) && !defined(TARGET_ABI32)
- _regs->gpr[2] = ldq_raw(infop->entry + 8) + infop->load_bias;
- infop->entry = ldq_raw(infop->entry) + infop->load_bias;
+ if (get_ppc64_abi(infop) < 2) {
+ _regs->gpr[2] = ldq_raw(infop->entry + 8) + infop->load_bias;
+ infop->entry = ldq_raw(infop->entry) + infop->load_bias;
+ } else {
+ _regs->gpr[12] = infop->entry; /* r12 set to global entry address */
+ }
#endif
_regs->nip = infop->entry;
}
target_ulong ccr = 0;
for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
- (*regs)[i] = tswapl(env->gpr[i]);
+ (*regs)[i] = tswapreg(env->gpr[i]);
}
- (*regs)[32] = tswapl(env->nip);
- (*regs)[33] = tswapl(env->msr);
- (*regs)[35] = tswapl(env->ctr);
- (*regs)[36] = tswapl(env->lr);
- (*regs)[37] = tswapl(env->xer);
+ (*regs)[32] = tswapreg(env->nip);
+ (*regs)[33] = tswapreg(env->msr);
+ (*regs)[35] = tswapreg(env->ctr);
+ (*regs)[36] = tswapreg(env->lr);
+ (*regs)[37] = tswapreg(env->xer);
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
ccr |= env->crf[i] << (32 - ((i + 1) * 4));
}
- (*regs)[38] = tswapl(ccr);
+ (*regs)[38] = tswapreg(ccr);
}
#define USE_ELF_CORE_DUMP
(*regs)[TARGET_EF_R0] = 0;
for (i = 1; i < ARRAY_SIZE(env->active_tc.gpr); i++) {
- (*regs)[TARGET_EF_R0 + i] = tswapl(env->active_tc.gpr[i]);
+ (*regs)[TARGET_EF_R0 + i] = tswapreg(env->active_tc.gpr[i]);
}
(*regs)[TARGET_EF_R26] = 0;
(*regs)[TARGET_EF_R27] = 0;
- (*regs)[TARGET_EF_LO] = tswapl(env->active_tc.LO[0]);
- (*regs)[TARGET_EF_HI] = tswapl(env->active_tc.HI[0]);
- (*regs)[TARGET_EF_CP0_EPC] = tswapl(env->active_tc.PC);
- (*regs)[TARGET_EF_CP0_BADVADDR] = tswapl(env->CP0_BadVAddr);
- (*regs)[TARGET_EF_CP0_STATUS] = tswapl(env->CP0_Status);
- (*regs)[TARGET_EF_CP0_CAUSE] = tswapl(env->CP0_Cause);
+ (*regs)[TARGET_EF_LO] = tswapreg(env->active_tc.LO[0]);
+ (*regs)[TARGET_EF_HI] = tswapreg(env->active_tc.HI[0]);
+ (*regs)[TARGET_EF_CP0_EPC] = tswapreg(env->active_tc.PC);
+ (*regs)[TARGET_EF_CP0_BADVADDR] = tswapreg(env->CP0_BadVAddr);
+ (*regs)[TARGET_EF_CP0_STATUS] = tswapreg(env->CP0_Status);
+ (*regs)[TARGET_EF_CP0_CAUSE] = tswapreg(env->CP0_Cause);
}
#define USE_ELF_CORE_DUMP
int i, pos = 0;
for (i = 0; i < 32; i++) {
- (*regs)[pos++] = tswapl(env->regs[i]);
+ (*regs)[pos++] = tswapreg(env->regs[i]);
}
for (i = 0; i < 6; i++) {
- (*regs)[pos++] = tswapl(env->sregs[i]);
+ (*regs)[pos++] = tswapreg(env->sregs[i]);
}
}
int i;
for (i = 0; i < 32; i++) {
- (*regs)[i] = tswapl(env->gpr[i]);
+ (*regs)[i] = tswapreg(env->gpr[i]);
}
- (*regs)[32] = tswapl(env->pc);
- (*regs)[33] = tswapl(env->sr);
+ (*regs)[32] = tswapreg(env->pc);
+ (*regs)[33] = tswapreg(env->sr);
}
#define ELF_HWCAP 0
#define ELF_PLATFORM NULL
int i;
for (i = 0; i < 16; i++) {
- (*regs[i]) = tswapl(env->gregs[i]);
+ (*regs[i]) = tswapreg(env->gregs[i]);
}
- (*regs)[TARGET_REG_PC] = tswapl(env->pc);
- (*regs)[TARGET_REG_PR] = tswapl(env->pr);
- (*regs)[TARGET_REG_SR] = tswapl(env->sr);
- (*regs)[TARGET_REG_GBR] = tswapl(env->gbr);
- (*regs)[TARGET_REG_MACH] = tswapl(env->mach);
- (*regs)[TARGET_REG_MACL] = tswapl(env->macl);
+ (*regs)[TARGET_REG_PC] = tswapreg(env->pc);
+ (*regs)[TARGET_REG_PR] = tswapreg(env->pr);
+ (*regs)[TARGET_REG_SR] = tswapreg(env->sr);
+ (*regs)[TARGET_REG_GBR] = tswapreg(env->gbr);
+ (*regs)[TARGET_REG_MACH] = tswapreg(env->mach);
+ (*regs)[TARGET_REG_MACL] = tswapreg(env->macl);
(*regs)[TARGET_REG_SYSCALL] = 0; /* FIXME */
}
static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUM68KState *env)
{
- (*regs)[0] = tswapl(env->dregs[1]);
- (*regs)[1] = tswapl(env->dregs[2]);
- (*regs)[2] = tswapl(env->dregs[3]);
- (*regs)[3] = tswapl(env->dregs[4]);
- (*regs)[4] = tswapl(env->dregs[5]);
- (*regs)[5] = tswapl(env->dregs[6]);
- (*regs)[6] = tswapl(env->dregs[7]);
- (*regs)[7] = tswapl(env->aregs[0]);
- (*regs)[8] = tswapl(env->aregs[1]);
- (*regs)[9] = tswapl(env->aregs[2]);
- (*regs)[10] = tswapl(env->aregs[3]);
- (*regs)[11] = tswapl(env->aregs[4]);
- (*regs)[12] = tswapl(env->aregs[5]);
- (*regs)[13] = tswapl(env->aregs[6]);
- (*regs)[14] = tswapl(env->dregs[0]);
- (*regs)[15] = tswapl(env->aregs[7]);
- (*regs)[16] = tswapl(env->dregs[0]); /* FIXME: orig_d0 */
- (*regs)[17] = tswapl(env->sr);
- (*regs)[18] = tswapl(env->pc);
+ (*regs)[0] = tswapreg(env->dregs[1]);
+ (*regs)[1] = tswapreg(env->dregs[2]);
+ (*regs)[2] = tswapreg(env->dregs[3]);
+ (*regs)[3] = tswapreg(env->dregs[4]);
+ (*regs)[4] = tswapreg(env->dregs[5]);
+ (*regs)[5] = tswapreg(env->dregs[6]);
+ (*regs)[6] = tswapreg(env->dregs[7]);
+ (*regs)[7] = tswapreg(env->aregs[0]);
+ (*regs)[8] = tswapreg(env->aregs[1]);
+ (*regs)[9] = tswapreg(env->aregs[2]);
+ (*regs)[10] = tswapreg(env->aregs[3]);
+ (*regs)[11] = tswapreg(env->aregs[4]);
+ (*regs)[12] = tswapreg(env->aregs[5]);
+ (*regs)[13] = tswapreg(env->aregs[6]);
+ (*regs)[14] = tswapreg(env->dregs[0]);
+ (*regs)[15] = tswapreg(env->aregs[7]);
+ (*regs)[16] = tswapreg(env->dregs[0]); /* FIXME: orig_d0 */
+ (*regs)[17] = tswapreg(env->sr);
+ (*regs)[18] = tswapreg(env->pc);
(*regs)[19] = 0; /* FIXME: regs->format | regs->vector */
}
#include "elf.h"
+#ifdef TARGET_PPC
+static inline uint32_t get_ppc64_abi(struct image_info *infop)
+{
+ return infop->elf_flags & EF_PPC64_ABI;
+}
+#endif
+
struct exec
{
unsigned int a_info; /* Use macros N_MAGIC, etc for access */
#define TARGET_ELF_PAGESTART(_v) ((_v) & ~(unsigned long)(TARGET_ELF_EXEC_PAGESIZE-1))
#define TARGET_ELF_PAGEOFFSET(_v) ((_v) & (TARGET_ELF_EXEC_PAGESIZE-1))
-#define DLINFO_ITEMS 13
+#define DLINFO_ITEMS 14
static inline void memcpy_fromfs(void * to, const void * from, unsigned long n)
{
return (elf_check_arch(ehdr->e_machine)
&& ehdr->e_ehsize == sizeof(struct elfhdr)
&& ehdr->e_phentsize == sizeof(struct elf_phdr)
- && ehdr->e_shentsize == sizeof(struct elf_shdr)
&& (ehdr->e_type == ET_EXEC || ehdr->e_type == ET_DYN));
}
perror("cannot mmap brk");
exit(-1);
}
+ }
- /* Since we didn't use target_mmap, make sure to record
- the validity of the pages with qemu. */
- page_set_flags(elf_bss & TARGET_PAGE_MASK, last_bss, prot|PAGE_VALID);
+ /* Ensure that the bss page(s) are valid */
+ if ((page_get_flags(last_bss-1) & prot) != prot) {
+ page_set_flags(elf_bss & TARGET_PAGE_MASK, last_bss, prot | PAGE_VALID);
}
if (host_start < host_map_start) {
size += 2;
#ifdef DLINFO_ARCH_ITEMS
size += DLINFO_ARCH_ITEMS * 2;
+#endif
+#ifdef ELF_HWCAP2
+ size += 2;
#endif
size += envc + argc + 2;
size += 1; /* argc itself */
NEW_AUX_ENT(AT_PHDR, (abi_ulong)(info->load_addr + exec->e_phoff));
NEW_AUX_ENT(AT_PHENT, (abi_ulong)(sizeof (struct elf_phdr)));
NEW_AUX_ENT(AT_PHNUM, (abi_ulong)(exec->e_phnum));
- NEW_AUX_ENT(AT_PAGESZ, (abi_ulong)(TARGET_PAGE_SIZE));
+ NEW_AUX_ENT(AT_PAGESZ, (abi_ulong)(MAX(TARGET_PAGE_SIZE, getpagesize())));
NEW_AUX_ENT(AT_BASE, (abi_ulong)(interp_info ? interp_info->load_addr : 0));
NEW_AUX_ENT(AT_FLAGS, (abi_ulong)0);
NEW_AUX_ENT(AT_ENTRY, info->entry);
NEW_AUX_ENT(AT_CLKTCK, (abi_ulong) sysconf(_SC_CLK_TCK));
NEW_AUX_ENT(AT_RANDOM, (abi_ulong) u_rand_bytes);
+#ifdef ELF_HWCAP2
+ NEW_AUX_ENT(AT_HWCAP2, (abi_ulong) ELF_HWCAP2);
+#endif
+
if (k_platform)
NEW_AUX_ENT(AT_PLATFORM, u_platform);
#ifdef ARCH_DLINFO
info->auxv_len = sp_auxv - sp;
sp = loader_build_argptr(envc, argc, sp, p, 0);
+ /* Check the right amount of stack was allocated for auxvec, envp & argv. */
+ assert(sp_auxv - sp == size);
return sp;
}
free(syms);
}
-int load_elf_binary(struct linux_binprm * bprm, struct target_pt_regs * regs,
- struct image_info * info)
+int load_elf_binary(struct linux_binprm *bprm, struct image_info *info)
{
struct image_info interp_info;
struct elfhdr elf_ex;
};
struct target_elf_siginfo {
- target_int si_signo; /* signal number */
- target_int si_code; /* extra code */
- target_int si_errno; /* errno */
+ abi_int si_signo; /* signal number */
+ abi_int si_code; /* extra code */
+ abi_int si_errno; /* errno */
};
struct target_elf_prstatus {
struct target_elf_siginfo pr_info; /* Info associated with signal */
- target_short pr_cursig; /* Current signal */
- target_ulong pr_sigpend; /* XXX */
- target_ulong pr_sighold; /* XXX */
+ abi_short pr_cursig; /* Current signal */
+ abi_ulong pr_sigpend; /* XXX */
+ abi_ulong pr_sighold; /* XXX */
target_pid_t pr_pid;
target_pid_t pr_ppid;
target_pid_t pr_pgrp;
struct target_timeval pr_cutime; /* XXX Cumulative user time */
struct target_timeval pr_cstime; /* XXX Cumulative system time */
target_elf_gregset_t pr_reg; /* GP registers */
- target_int pr_fpvalid; /* XXX */
+ abi_int pr_fpvalid; /* XXX */
};
#define ELF_PRARGSZ (80) /* Number of chars for args */
char pr_sname; /* char for pr_state */
char pr_zomb; /* zombie */
char pr_nice; /* nice val */
- target_ulong pr_flag; /* flags */
+ abi_ulong pr_flag; /* flags */
target_uid_t pr_uid;
target_gid_t pr_gid;
target_pid_t pr_pid, pr_ppid, pr_pgrp, pr_sid;
#ifdef BSWAP_NEEDED
static void bswap_prstatus(struct target_elf_prstatus *prstatus)
{
- prstatus->pr_info.si_signo = tswapl(prstatus->pr_info.si_signo);
- prstatus->pr_info.si_code = tswapl(prstatus->pr_info.si_code);
- prstatus->pr_info.si_errno = tswapl(prstatus->pr_info.si_errno);
+ prstatus->pr_info.si_signo = tswap32(prstatus->pr_info.si_signo);
+ prstatus->pr_info.si_code = tswap32(prstatus->pr_info.si_code);
+ prstatus->pr_info.si_errno = tswap32(prstatus->pr_info.si_errno);
prstatus->pr_cursig = tswap16(prstatus->pr_cursig);
- prstatus->pr_sigpend = tswapl(prstatus->pr_sigpend);
- prstatus->pr_sighold = tswapl(prstatus->pr_sighold);
+ prstatus->pr_sigpend = tswapal(prstatus->pr_sigpend);
+ prstatus->pr_sighold = tswapal(prstatus->pr_sighold);
prstatus->pr_pid = tswap32(prstatus->pr_pid);
prstatus->pr_ppid = tswap32(prstatus->pr_ppid);
prstatus->pr_pgrp = tswap32(prstatus->pr_pgrp);
static void bswap_psinfo(struct target_elf_prpsinfo *psinfo)
{
- psinfo->pr_flag = tswapl(psinfo->pr_flag);
+ psinfo->pr_flag = tswapal(psinfo->pr_flag);
psinfo->pr_uid = tswap16(psinfo->pr_uid);
psinfo->pr_gid = tswap16(psinfo->pr_gid);
psinfo->pr_pid = tswap32(psinfo->pr_pid);
static void fill_thread_info(struct elf_note_info *info, const CPUArchState *env)
{
- TaskState *ts = (TaskState *)env->opaque;
+ CPUState *cpu = ENV_GET_CPU((CPUArchState *)env);
+ TaskState *ts = (TaskState *)cpu->opaque;
struct elf_thread_status *ets;
ets = g_malloc0(sizeof (*ets));
info->notes_size += note_size(&ets->notes[0]);
}
+static void init_note_info(struct elf_note_info *info)
+{
+ /* Initialize the elf_note_info structure so that it is at
+ * least safe to call free_note_info() on it. Must be
+ * called before calling fill_note_info().
+ */
+ memset(info, 0, sizeof (*info));
+ QTAILQ_INIT(&info->thread_list);
+}
+
static int fill_note_info(struct elf_note_info *info,
long signr, const CPUArchState *env)
{
#define NUMNOTES 3
- CPUArchState *cpu = NULL;
- TaskState *ts = (TaskState *)env->opaque;
+ CPUState *cpu = ENV_GET_CPU((CPUArchState *)env);
+ TaskState *ts = (TaskState *)cpu->opaque;
int i;
- (void) memset(info, 0, sizeof (*info));
-
- QTAILQ_INIT(&info->thread_list);
-
info->notes = g_malloc0(NUMNOTES * sizeof (struct memelfnote));
if (info->notes == NULL)
return (-ENOMEM);
/* read and fill status of all threads */
cpu_list_lock();
- for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) {
- if (cpu == thread_env)
+ CPU_FOREACH(cpu) {
+ if (cpu == thread_cpu) {
continue;
- fill_thread_info(info, cpu);
+ }
+ fill_thread_info(info, (CPUArchState *)cpu->env_ptr);
}
cpu_list_unlock();
*/
static int elf_core_dump(int signr, const CPUArchState *env)
{
- const TaskState *ts = (const TaskState *)env->opaque;
+ const CPUState *cpu = ENV_GET_CPU((CPUArchState *)env);
+ const TaskState *ts = (const TaskState *)cpu->opaque;
struct vm_area_struct *vma = NULL;
char corefile[PATH_MAX];
struct elf_note_info info;
int segs = 0;
int fd = -1;
+ init_note_info(&info);
+
errno = 0;
getrlimit(RLIMIT_CORE, &dumpsize);
if (dumpsize.rlim_cur == 0)
projects / mirror_qemu.git / blobdiff