your customers the hassle of this boot option.
Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
+Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
---
- Documentation/admin-guide/kernel-parameters.txt | 9 +++
- drivers/pci/quirks.c | 101 ++++++++++++++++++++++++
- 2 files changed, 110 insertions(+)
+ .../admin-guide/kernel-parameters.txt | 9 ++
+ drivers/pci/quirks.c | 102 ++++++++++++++++++
+ 2 files changed, 111 insertions(+)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
-index 51210d10d905..ceb1b471d249 100644
+index c73168dbb050..754fa5793a4d 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
-@@ -3049,6 +3049,15 @@
- nomsi [MSI] If the PCI_MSI kernel config parameter is
- enabled, this kernel boot option can be used to
- disable the use of MSI interrupts system-wide.
+@@ -3943,6 +3943,15 @@
+ Also, it enforces the PCI Local Bus spec
+ rule that those bits should be 0 in system reset
+ events (useful for kexec/kdump cases).
+ pci_acs_override =
-+ [PCIE] Override missing PCIe ACS support for:
++ [PCIE] Override missing PCIe ACS support for:
+ downstream
+ All downstream ports - full ACS capabilities
+ multifunction
Safety option to keep boot IRQs enabled. This
should never be necessary.
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
-index 2953239fa628..b2c9428b13a3 100644
+index 1c566b0cbee9..d49c54c579bb 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
-@@ -3702,6 +3702,106 @@ static int __init pci_apply_final_quirks(void)
-
+@@ -193,6 +193,106 @@ static int __init pci_apply_final_quirks(void)
+ }
fs_initcall_sync(pci_apply_final_quirks);
+static bool acs_on_downstream;
+}
+
/*
- * Following are device-specific reset methods which can be used to
- * reset a single function if other methods (e.g. FLR, PM D0->D3) are
-@@ -4541,6 +4641,7 @@ static const struct pci_dev_acs_enabled {
- { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
+ * Decoding should be disabled for a PCI device during BAR sizing to avoid
+ * conflict. But doing so may cause problems on host bridge and perhaps other
+@@ -4927,6 +5027,8 @@ static const struct pci_dev_acs_enabled {
+ { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
/* APM X-Gene */
{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
++ /* Enable overrides for missing ACS capabilities */
+ { PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
- { 0 }
- };
-
+ /* Ampere Computing */
+ { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
+ { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },