target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode

[mirror_qemu.git] / qemu-edid.c

diff --git a/qemu-edid.c b/qemu-edid.c
index 1cd6a95172388924c87d00446fd234e6cf8c2a6a..c3a9fba10dc494e404eb461f34bec369b950bccf 100644 (file)
--- a/qemu-edid.c
+++ b/qemu-edid.c
@@ -41,7 +41,8 @@ static void usage(FILE *out)
 int main(int argc, char *argv[])
 {
     FILE *outfile = NULL;
-    uint8_t blob[256];
+    uint8_t blob[512];
+    size_t size;
     uint32_t dpi = 100;
     int rc;
 
@@ -119,7 +120,8 @@ int main(int argc, char *argv[])
 
     memset(blob, 0, sizeof(blob));
     qemu_edid_generate(blob, sizeof(blob), &info);
-    fwrite(blob, sizeof(blob), 1, outfile);
+    size = qemu_edid_size(blob);
+    fwrite(blob, size, 1, outfile);
     fflush(outfile);
 
     exit(0);