# This work is licensed under the terms of the GNU GPL, version 2. See
# the COPYING file in the top-level directory.
+from __future__ import print_function
MSR_IA32_VMX_BASIC = 0x480
MSR_IA32_VMX_PINBASED_CTLS = 0x481
MSR_IA32_VMX_PROCBASED_CTLS = 0x482
class msr(object):
def __init__(self):
try:
- self.f = open('/dev/cpu/0/msr', 'r', 0)
+ self.f = open('/dev/cpu/0/msr', 'rb', 0)
except:
- self.f = open('/dev/msr0', 'r', 0)
+ self.f = open('/dev/msr0', 'rb', 0)
def read(self, index, default = None):
import struct
self.f.seek(index)
val = m.read(nr, 0)
return (val & 0xffffffff, val >> 32)
def show(self):
- print self.name
+ print(self.name)
mbz, mb1 = self.read2(self.cap_msr)
tmbz, tmb1 = 0, 0
if self.true_cap_msr:
s = 'forced'
elif one and zero:
s = 'yes'
- print ' %-40s %s' % (self.bits[bit], s)
+ print(' %-40s %s' % (self.bits[bit], s))
class Misc(object):
def __init__(self, name, bits, msr):
self.bits = bits
self.msr = msr
def show(self):
- print self.name
+ print(self.name)
value = msr().read(self.msr, 0)
+ print(' Hex: 0x%x' % (value))
def first_bit(key):
if type(key) is tuple:
return key[0]
def fmt(x):
return { True: 'yes', False: 'no' }[x]
v = (value >> lo) & ((1 << (hi - lo + 1)) - 1)
- print ' %-40s %s' % (self.bits[bits], fmt(v))
+ print(' %-40s %s' % (self.bits[bits], fmt(v)))
controls = [
Misc(
name = 'Basic VMX Information',
bits = {
- (0, 31): 'Revision',
+ (0, 30): 'Revision',
(32,44): 'VMCS size',
48: 'VMCS restricted to 32 bit addresses',
49: 'Dual-monitor support',
12: 'Enable INVPCID',
13: 'Enable VM functions',
14: 'VMCS shadowing',
- 18: 'EPT-violation #VE'
+ 15: 'Enable ENCLS exiting',
+ 16: 'RDSEED exiting',
+ 17: 'Enable PML',
+ 18: 'EPT-violation #VE',
+ 19: 'Conceal non-root operation from PT',
+ 20: 'Enable XSAVES/XRSTORS',
+ 22: 'Mode-based execute control (XS/XU)',
+ 23: 'Sub-page write permissions',
+ 24: 'GPA translation for PT',
+ 25: 'TSC scaling',
+ 26: 'User wait and pause',
+ 28: 'ENCLV exiting',
},
cap_msr = MSR_IA32_VMX_PROCBASED_CTLS2,
),
20: 'Save IA32_EFER',
21: 'Load IA32_EFER',
22: 'Save VMX-preemption timer value',
+ 23: 'Clear IA32_BNDCFGS',
+ 24: 'Conceal VM exits from PT',
+ 25: 'Clear IA32_RTIT_CTL',
},
cap_msr = MSR_IA32_VMX_EXIT_CTLS,
true_cap_msr = MSR_IA32_VMX_TRUE_EXIT_CTLS,
name = 'VM-Entry controls',
bits = {
2: 'Load debug controls',
- 9: 'IA-64 mode guest',
+ 9: 'IA-32e mode guest',
10: 'Entry to SMM',
11: 'Deactivate dual-monitor treatment',
13: 'Load IA32_PERF_GLOBAL_CTRL',
14: 'Load IA32_PAT',
15: 'Load IA32_EFER',
+ 16: 'Load IA32_BNDCFGS',
+ 17: 'Conceal VM entries from PT',
+ 18: 'Load IA32_RTIT_CTL',
},
cap_msr = MSR_IA32_VMX_ENTRY_CTLS,
true_cap_msr = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
6: 'HLT activity state',
7: 'Shutdown activity state',
8: 'Wait-for-SIPI activity state',
+ 14: 'PT in VMX operation',
15: 'IA32_SMBASE support',
(16,24): 'Number of CR3-target values',
- (25,27): 'MSR-load/store count recommenation',
+ (25,27): 'MSR-load/store count recommendation',
28: 'IA32_SMM_MONITOR_CTL[2] can be set to 1',
29: 'VMWRITE to VM-exit information fields',
+ 30: 'Inject event with insn length=0',
(32,63): 'MSEG revision identifier',
},
msr = MSR_IA32_VMX_MISC_CTLS,
17: '1GB EPT pages',
20: 'INVEPT supported',
21: 'EPT accessed and dirty flags',
+ 22: 'Advanced VM-exit information for EPT violations',
25: 'Single-context INVEPT',
26: 'All-context INVEPT',
32: 'INVVPID supported',