{ "v8", MASK_V6 | MASK_V7 | MASK_V8 },
{ "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
{ "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
- /* ??? Don't some v8 priviledged insns conflict with v9? */
+ /* ??? Don't some v8 privileged insns conflict with v9? */
{ "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
/* v9 with ultrasparc additions */
{ "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
#define FBFCC(x) (((x)&0x3)<<20) /* v9 */
\f
/* The order of the opcodes in the table is significant:
-
+
* The assembler requires that all instances of the same mnemonic must
be consecutive. If they aren't, the assembler will bomb at runtime.
\f
/* Handle ASI's. */
-static arg asi_table[] =
+static const arg asi_table_v8[] =
+{
+ { 0x00, "#ASI_M_RES00" },
+ { 0x01, "#ASI_M_UNA01" },
+ { 0x02, "#ASI_M_MXCC" },
+ { 0x03, "#ASI_M_FLUSH_PROBE" },
+ { 0x04, "#ASI_M_MMUREGS" },
+ { 0x05, "#ASI_M_TLBDIAG" },
+ { 0x06, "#ASI_M_DIAGS" },
+ { 0x07, "#ASI_M_IODIAG" },
+ { 0x08, "#ASI_M_USERTXT" },
+ { 0x09, "#ASI_M_KERNELTXT" },
+ { 0x0A, "#ASI_M_USERDATA" },
+ { 0x0B, "#ASI_M_KERNELDATA" },
+ { 0x0C, "#ASI_M_TXTC_TAG" },
+ { 0x0D, "#ASI_M_TXTC_DATA" },
+ { 0x0E, "#ASI_M_DATAC_TAG" },
+ { 0x0F, "#ASI_M_DATAC_DATA" },
+ { 0x10, "#ASI_M_FLUSH_PAGE" },
+ { 0x11, "#ASI_M_FLUSH_SEG" },
+ { 0x12, "#ASI_M_FLUSH_REGION" },
+ { 0x13, "#ASI_M_FLUSH_CTX" },
+ { 0x14, "#ASI_M_FLUSH_USER" },
+ { 0x17, "#ASI_M_BCOPY" },
+ { 0x18, "#ASI_M_IFLUSH_PAGE" },
+ { 0x19, "#ASI_M_IFLUSH_SEG" },
+ { 0x1A, "#ASI_M_IFLUSH_REGION" },
+ { 0x1B, "#ASI_M_IFLUSH_CTX" },
+ { 0x1C, "#ASI_M_IFLUSH_USER" },
+ { 0x1F, "#ASI_M_BFILL" },
+ { 0x20, "#ASI_M_BYPASS" },
+ { 0x29, "#ASI_M_FBMEM" },
+ { 0x2A, "#ASI_M_VMEUS" },
+ { 0x2B, "#ASI_M_VMEPS" },
+ { 0x2C, "#ASI_M_VMEUT" },
+ { 0x2D, "#ASI_M_VMEPT" },
+ { 0x2E, "#ASI_M_SBUS" },
+ { 0x2F, "#ASI_M_CTL" },
+ { 0x31, "#ASI_M_FLUSH_IWHOLE" },
+ { 0x36, "#ASI_M_IC_FLCLEAR" },
+ { 0x37, "#ASI_M_DC_FLCLEAR" },
+ { 0x39, "#ASI_M_DCDR" },
+ { 0x40, "#ASI_M_VIKING_TMP1" },
+ { 0x41, "#ASI_M_VIKING_TMP2" },
+ { 0x4c, "#ASI_M_ACTION" },
+ { 0, 0 }
+};
+
+static const arg asi_table_v9[] =
{
/* These are in the v9 architecture manual. */
/* The shorter versions appear first, they're here because Sun's as has them.
{ 0, 0 }
};
-/* Return the value for ASI NAME, or -1 if not found. */
+/* Return the name for ASI value VALUE or NULL if not found. */
-int
-sparc_encode_asi (name)
- const char *name;
+static const char *
+sparc_decode_asi_v9 (int value)
{
- return lookup_name (asi_table, name);
+ return lookup_value (asi_table_v9, value);
}
-/* Return the name for ASI value VALUE or NULL if not found. */
-
-const char *
-sparc_decode_asi (value)
- int value;
+static const char *
+sparc_decode_asi_v8 (int value)
{
- return lookup_value (asi_table, value);
+ return lookup_value (asi_table_v8, value);
}
\f
/* Handle membar masks. */
-static arg membar_table[] =
+static const arg membar_table[] =
{
{ 0x40, "#Sync" },
{ 0x20, "#MemIssue" },
\f
/* Handle prefetch args. */
-static arg prefetch_table[] =
+static const arg prefetch_table[] =
{
{ 0, "#n_reads" },
{ 1, "#one_read" },
\f
/* Handle sparclet coprocessor registers. */
-static arg sparclet_cpreg_table[] =
+static const arg sparclet_cpreg_table[] =
{
{ 0, "%ccsr" },
{ 1, "%ccfr" },
/* It is important that we only look at insn code bits as that is how the
opcode table is hashed. OPCODE_BITS is a table of valid bits for each
of the main types (0,1,2,3). */
-static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
+static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
#define HASH_INSN(INSN) \
((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
struct opcode_hash {
((((int)(value)) << ((8 * sizeof (int)) - bits)) \
>> ((8 * sizeof (int)) - bits) )
-static char *reg_names[] =
-{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
- "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
- "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
- "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
- "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+static const char * const reg_names[] =
+{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
+ "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+ "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
- "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
- "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
+ "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
+ "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
"f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
"f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
/* psr, wim, tbr, fpsr, cpsr are v8 only. */
/* These are ordered according to there register number in
rdpr and wrpr insns. */
-static char *v9_priv_reg_names[] =
+static const char * const v9_priv_reg_names[] =
{
"tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
/* These are ordered according to there register number in
rd and wr insns (-16). */
-static char *v9a_asr_reg_names[] =
+static const char * const v9a_asr_reg_names[] =
{
"pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
"softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
/* Nonzero means that we have found a plus sign in the args
field of the opcode table. */
int found_plus = 0;
-
+
/* Nonzero means we have an annulled branch. */
int is_annulled = 0;
} /* while there are comma started args */
(*info->fprintf_func) (stream, " ");
-
+
switch (*s)
{
case '+':
not before it. */
if (found_plus)
imm_added_to_rs1 = 1;
-
+
if (imm <= 9)
(*info->fprintf_func) (stream, "%d", imm);
else
case 'o':
(*info->fprintf_func) (stream, "%%asi");
break;
-
+
case 'W':
(*info->fprintf_func) (stream, "%%tick");
break;
(*info->fprintf_func) (stream, "%d", X_RD (insn));
break;
}
-
+
case 'M':
(*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
break;
-
+
case 'm':
(*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
break;
-
+
case 'L':
info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
(*info->print_address_func) (info->target, info);
case 'A':
{
- const char *name = sparc_decode_asi (X_ASI (insn));
+ const char *name;
+
+ if ((info->mach == bfd_mach_sparc_v8plusa) ||
+ ((info->mach >= bfd_mach_sparc_v9) &&
+ (info->mach <= bfd_mach_sparc_v9b)))
+ name = sparc_decode_asi_v9 (X_ASI (insn));
+ else
+ name = sparc_decode_asi_v8 (X_ASI (insn));
if (name)
(*info->fprintf_func) (stream, "%s", name);
&& X_RD (prev_insn) == X_RS1 (insn))
{
(*info->fprintf_func) (stream, "\t! ");
- info->target =
+ info->target =
((unsigned) 0xFFFFFFFF
& ((int) X_IMM22 (prev_insn) << 10));
if (imm_added_to_rs1)
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