/* Collect the set of vector lengths supported by KVM. */
bitmap_zero(kvm_supported, ARM_MAX_VQ);
- if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) {
+ if (kvm_enabled() && kvm_arm_sve_supported()) {
kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
} else if (kvm_enabled()) {
assert(!cpu_isar_feature(aa64_sve, cpu));
void *opaque, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
- Error *err = NULL;
uint32_t max_vq;
- visit_type_uint32(v, name, &max_vq, &err);
- if (err) {
- error_propagate(errp, err);
+ if (!visit_type_uint32(v, name, &max_vq, errp)) {
return;
}
- if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+ if (kvm_enabled() && !kvm_arm_sve_supported()) {
error_setg(errp, "cannot set sve-max-vq");
error_append_hint(errp, "SVE not supported by KVM on this host\n");
return;
{
ARMCPU *cpu = ARM_CPU(obj);
uint32_t vq = atoi(&name[3]) / 128;
- Error *err = NULL;
bool value;
- visit_type_bool(v, name, &value, &err);
- if (err) {
- error_propagate(errp, err);
+ if (!visit_type_bool(v, name, &value, errp)) {
return;
}
- if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+ if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
error_setg(errp, "cannot enable %s", name);
error_append_hint(errp, "SVE not supported by KVM on this host\n");
return;
void *opaque, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
- Error *err = NULL;
bool value;
uint64_t t;
- visit_type_bool(v, name, &value, &err);
- if (err) {
- error_propagate(errp, err);
+ if (!visit_type_bool(v, name, &value, errp)) {
return;
}
- if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+ if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
error_setg(errp, "'sve' feature not supported by KVM on this host");
return;
}
uint32_t vq;
object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
- cpu_arm_set_sve, NULL, NULL, &error_fatal);
+ cpu_arm_set_sve, NULL, NULL);
for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
char name[8];
sprintf(name, "sve%d", vq * 128);
object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
- cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
+ cpu_arm_set_sve_vq, NULL, NULL);
}
}
if (kvm_enabled()) {
kvm_arm_set_cpu_features_from_host(cpu);
- kvm_arm_add_vcpu_properties(obj);
} else {
uint64_t t;
uint32_t u;
t = cpu->isar.id_aa64pfr1;
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
+ /*
+ * Begin with full support for MTE; will be downgraded to MTE=1
+ * during realize if the board provides no tag memory.
+ */
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
cpu->isar.id_aa64pfr1 = t;
t = cpu->isar.id_aa64mmfr1;
aarch64_add_sve_properties(obj);
object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
- cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
+ cpu_max_set_sve_max_vq, NULL, NULL);
}
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
{ .name = "max", .initfn = aarch64_max_initfn },
- { .name = NULL }
};
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
* uniform execution state like do_interrupt.
*/
if (value == false) {
- if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
+ if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
error_setg(errp, "'aarch64' feature cannot be disabled "
"unless KVM is enabled and 32-bit EL1 "
"is supported");
static void aarch64_cpu_initfn(Object *obj)
{
object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
- aarch64_cpu_set_aarch64, NULL);
+ aarch64_cpu_set_aarch64);
object_property_set_description(obj, "aarch64",
"Set on/off to enable/disable aarch64 "
- "execution state ",
- NULL);
+ "execution state ");
}
static void aarch64_cpu_finalizefn(Object *obj)
static void aarch64_cpu_register_types(void)
{
- const ARMCPUInfo *info = aarch64_cpus;
+ size_t i;
type_register_static(&aarch64_cpu_type_info);
- while (info->name) {
- aarch64_cpu_register(info);
- info++;
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
+ aarch64_cpu_register(&aarch64_cpus[i]);
}
}