target/arm: Complete TBI clearing for user-only for SVE

[mirror_qemu.git] / target / arm / translate-a64.c

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e46c4a49e00b4f7ff9ec36b7ab783621e317e8af..c20af6ee9d03b9be31b2c70a2cab53bcb86a918e 100644 (file)
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14634,6 +14634,11 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->features = env->features;
     dc->dcz_blocksize = arm_cpu->dcz_blocksize;
 
+#ifdef CONFIG_USER_ONLY
+    /* In sve_probe_page, we assume TBI is enabled. */
+    tcg_debug_assert(dc->tbid & 1);
+#endif
+
     /* Single step state. The code-generation logic here is:
      *  SS_ACTIVE == 0:
      *   generate code with no special handling for single-stepping (except