Hexagon (target/hexagon) Improve code gen for predicated HVX instructions

[mirror_qemu.git] / target / hexagon / gen_analyze_funcs.py

diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analyze_funcs.py
index 7e1f221b3c58324f72593c25e8b7d085ada5306a..ebd3e7afb91476553a39dfb3875dfdd9d6300323 100755 (executable)
--- a/target/hexagon/gen_analyze_funcs.py
+++ b/target/hexagon/gen_analyze_funcs.py
@@ -83,9 +83,16 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
         else:
             print("Bad register parse: ", regtype, regid)
     elif (regtype == "V"):
+        newv = "EXT_DFL"
+        if (hex_common.is_new_result(tag)):
+            newv = "EXT_NEW"
+        elif (hex_common.is_tmp_result(tag)):
+            newv = "EXT_TMP"
         if (regid in {"dd", "xx"}):
-            f.write("//    const int %s = insn->regno[%d];\n" %\
+            f.write("    const int %s = insn->regno[%d];\n" %\
                 (regN, regno))
+            f.write("    ctx_log_vreg_write_pair(ctx, %s, %s, %s);\n" % \
+                (regN, newv, predicated))
         elif (regid in {"uu", "vv"}):
             f.write("//    const int %s = insn->regno[%d];\n" % \
                 (regN, regno))
@@ -93,14 +100,17 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
             f.write("//    const int %s = insn->regno[%d];\n" % \
                 (regN, regno))
         elif (regid in {"d", "x", "y"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
+            f.write("    const int %s = insn->regno[%d];\n" % \
                 (regN, regno))
+            f.write("    ctx_log_vreg_write(ctx, %s, %s, %s);\n" % \
+                (regN, newv, predicated))
         else:
             print("Bad register parse: ", regtype, regid)
     elif (regtype == "Q"):
         if (regid in {"d", "e", "x"}):
-            f.write("//    const int %s = insn->regno[%d];\n" % \
+            f.write("    const int %s = insn->regno[%d];\n" % \
                 (regN, regno))
+            f.write("    ctx_log_qreg_write(ctx, %s);\n" % (regN))
         elif (regid in {"s", "t", "u", "v"}):
             f.write("//    const int %s = insn->regno[%d];\n" % \
                 (regN, regno))