basis. It's probably easier to fall back to a strong memory model. */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-#define MMU_KERNEL_IDX 7
-#define MMU_KERNEL_P_IDX 8
-#define MMU_PL1_IDX 9
-#define MMU_PL1_P_IDX 10
-#define MMU_PL2_IDX 11
-#define MMU_PL2_P_IDX 12
-#define MMU_USER_IDX 13
-#define MMU_USER_P_IDX 14
-#define MMU_PHYS_IDX 15
-
+#define MMU_ABS_W_IDX 6
+#define MMU_ABS_IDX 7
+#define MMU_KERNEL_IDX 8
+#define MMU_KERNEL_P_IDX 9
+#define MMU_PL1_IDX 10
+#define MMU_PL1_P_IDX 11
+#define MMU_PL2_IDX 12
+#define MMU_PL2_P_IDX 13
+#define MMU_USER_IDX 14
+#define MMU_USER_P_IDX 15
+
+#define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) < MMU_KERNEL_IDX)
#define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2)
#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
-#define TARGET_INSN_START_EXTRA_WORDS 1
+#define TARGET_INSN_START_EXTRA_WORDS 2
-/* No need to flush MMU_PHYS_IDX */
+/* No need to flush MMU_ABS*_IDX */
#define HPPA_MMU_FLUSH_MASK \
(1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \
1 << MMU_PL1_IDX | 1 << MMU_PL1_P_IDX | \
1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \
1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX)
-/* Indicies to flush for access_id changes. */
+/* Indices to flush for access_id changes. */
#define HPPA_MMU_FLUSH_P_MASK \
(1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \
1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX)
#define PSW_T 0x01000000
#define PSW_S 0x02000000
#define PSW_E 0x04000000
-#ifdef TARGET_HPPA64
#define PSW_W 0x08000000 /* PA2.0 only */
-#else
-#define PSW_W 0
-#endif
#define PSW_Z 0x40000000 /* PA1.x only */
#define PSW_Y 0x80000000 /* PA1.x only */
#define PSW_SM_P PSW_P
#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
-#ifdef TARGET_HPPA64
#define PSW_SM_E 0x100
#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
-#else
-#define PSW_SM_E 0
-#define PSW_SM_W 0
-#endif
#define CR_RC 0
+#define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */
+#define PDC_PSW_WIDE_BIT 2
#define CR_PID1 8
#define CR_PID2 9
#define CR_PID3 12
#define CR_IPSW 22
#define CR_EIRR 23
-#if TARGET_REGISTER_BITS == 32
-typedef uint32_t target_ureg;
-typedef int32_t target_sreg;
-#define TREG_FMT_lx "%08"PRIx32
-#define TREG_FMT_ld "%"PRId32
-#else
-typedef uint64_t target_ureg;
-typedef int64_t target_sreg;
-#define TREG_FMT_lx "%016"PRIx64
-#define TREG_FMT_ld "%"PRId64
-#endif
-
typedef struct HPPATLBEntry {
union {
IntervalTreeNode itree;
struct HPPATLBEntry *unused_next;
};
- target_ureg pa;
+ target_ulong pa;
unsigned entry_valid : 1;
} HPPATLBEntry;
typedef struct CPUArchState {
- target_ureg iaoq_f; /* front */
- target_ureg iaoq_b; /* back, aka next instruction */
+ target_ulong iaoq_f; /* front */
+ target_ulong iaoq_b; /* back, aka next instruction */
- target_ureg gr[32];
+ target_ulong gr[32];
uint64_t fr[32];
uint64_t sr[8]; /* stored shifted into place for gva */
- target_ureg psw; /* All psw bits except the following: */
- target_ureg psw_n; /* boolean */
- target_sreg psw_v; /* in most significant bit */
+ target_ulong psw; /* All psw bits except the following: */
+ target_ulong psw_n; /* boolean */
+ target_long psw_v; /* in most significant bit */
/* Splitting the carry-borrow field into the MSB and "the rest", allows
* for "the rest" to be deleted when it is unused, but the MSB is in use.
* host has the appropriate add-with-carry insn to compute the msb).
* Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
*/
- target_ureg psw_cb; /* in least significant bit of next nibble */
- target_ureg psw_cb_msb; /* boolean */
+ target_ulong psw_cb; /* in least significant bit of next nibble */
+ target_ulong psw_cb_msb; /* boolean */
uint64_t iasq_f;
uint64_t iasq_b;
uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */
float_status fp_status;
- target_ureg cr[32]; /* control registers */
- target_ureg cr_back[2]; /* back of cr17/cr18 */
- target_ureg shadow[7]; /* shadow registers */
+ target_ulong cr[32]; /* control registers */
+ target_ulong cr_back[2]; /* back of cr17/cr18 */
+ target_ulong shadow[7]; /* shadow registers */
+
+ /*
+ * During unwind of a memory insn, the base register of the address.
+ * This is used to construct CR_IOR for pa2.0.
+ */
+ uint32_t unwind_breg;
/*
* ??? The number of entries isn't specified by the architecture.
* An HPPA CPU.
*/
struct ArchCPU {
- /*< private >*/
CPUState parent_obj;
- /*< public >*/
CPUHPPAState env;
QEMUTimer *alarm_timer;
};
+/**
+ * HPPACPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An HPPA CPU model.
+ */
+struct HPPACPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ DeviceReset parent_reset;
+};
+
#include "exec/cpu-all.h"
static inline bool hppa_is_pa20(CPUHPPAState *env)
if (env->psw & (ifetch ? PSW_C : PSW_D)) {
return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
}
- return MMU_PHYS_IDX; /* mmu disabled */
+ /* mmu disabled */
+ return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX;
#endif
}
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
-static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
- target_ureg off)
+static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc,
+ target_ulong off)
{
#ifdef CONFIG_USER_ONLY
return off;
}
static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
- target_ureg off)
+ target_ulong off)
{
return hppa_form_gva_psw(env->psw, spc, off);
}
which is the primary case we care about -- using goto_tb within a page.
Failure is indicated by a zero difference. */
if (env->iasq_f == env->iasq_b) {
- target_sreg diff = env->iaoq_b - env->iaoq_f;
- if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
+ target_long diff = env->iaoq_b - env->iaoq_f;
+ if (diff == (int32_t)diff) {
*cs_base |= (uint32_t)diff;
}
}
*pflags = flags;
}
-target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
-void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
+target_ulong cpu_hppa_get_psw(CPUHPPAState *env);
+void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong);
void cpu_hppa_loaded_fr0(CPUHPPAState *env);
#ifdef CONFIG_USER_ONLY
#ifndef CONFIG_USER_ONLY
void hppa_ptlbe(CPUHPPAState *env);
hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
+void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled);
bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
-#define cpu_list hppa_cpu_list
-void hppa_cpu_list(void);
-
#endif /* HPPA_CPU_H */
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