#include "sysemu/reset.h"
#include "sysemu/hvf.h"
#include "sysemu/cpus.h"
+#include "sysemu/xen.h"
#include "kvm_i386.h"
#include "sev_i386.h"
#include "hw/i386/topology.h"
#ifndef CONFIG_USER_ONLY
#include "exec/address-spaces.h"
-#include "hw/xen/xen.h"
#include "hw/i386/apic_internal.h"
#include "hw/boards.h"
#endif
.feat_names = {
NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
NULL, NULL, NULL, NULL,
- NULL, NULL, "md-clear", NULL,
+ "avx512-vp2intersect", NULL, "md-clear", NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL /* pconfig */, NULL,
NULL, NULL, NULL, NULL,
.index = MSR_IA32_CORE_CAPABILITY,
},
},
+ [FEAT_PERF_CAPABILITIES] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, "full-width-write", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_PERF_CAPABILITIES,
+ },
+ },
[FEAT_VMX_PROCBASED_CTLS] = {
.type = MSR_FEATURE_WORD,
.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
.to = { FEAT_CORE_CAPABILITY, ~0ull },
},
+ {
+ .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
+ .to = { FEAT_PERF_CAPABILITIES, ~0ull },
+ },
{
.from = { FEAT_1_ECX, CPUID_EXT_VMX },
.to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
.from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
.to = { FEAT_VMX_VMFUNC, ~0ull },
},
+ {
+ .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
+ .to = { FEAT_SVM, ~0ull },
+ },
};
typedef struct X86RegisterInfo32 {
.versions = (X86CPUVersionDefinition[]) {
{ .version = 1 },
{ .version = 2,
+ .note = "ARCH_CAPABILITIES",
.props = (PropValue[]) {
{ "arch-capabilities", "on" },
{ "rdctl-no", "on" },
},
{ .version = 3,
.alias = "Cascadelake-Server-noTSX",
+ .note = "ARCH_CAPABILITIES, no TSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
{ .version = 1 },
{
.version = 2,
+ .note = "no TSX",
.alias = "Icelake-Client-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ .version = 1 },
{
.version = 2,
+ .note = "no TSX",
.alias = "Icelake-Server-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ .version = 1 },
{
.version = 2,
+ .note = "no MPX, no MONITOR",
.props = (PropValue[]) {
{ "monitor", "off" },
{ "mpx", "off" },
host_vendor_fms(vendor, &family, &model, &stepping);
cpu_x86_fill_model_id(model_id);
- object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
- object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
- object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
- object_property_set_int(OBJECT(cpu), stepping, "stepping",
+ object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
+ object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
+ object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
+ object_property_set_int(OBJECT(cpu), "stepping", stepping,
&error_abort);
- object_property_set_str(OBJECT(cpu), model_id, "model-id",
+ object_property_set_str(OBJECT(cpu), "model-id", model_id,
&error_abort);
if (kvm_enabled()) {
}
if (lmce_supported()) {
- object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
+ object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
}
} else {
- object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
- "vendor", &error_abort);
- object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
- object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
- object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
- object_property_set_str(OBJECT(cpu),
+ object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
+ &error_abort);
+ object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
+ object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
+ object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
+ object_property_set_str(OBJECT(cpu), "model-id",
"QEMU TCG CPU version " QEMU_HW_VERSION,
- "model-id", &error_abort);
+ &error_abort);
}
- object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
+ object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
}
static const TypeInfo max_x86_cpu_type_info = {
CPUX86State *env = &cpu->env;
const int64_t min = 0;
const int64_t max = 0xff + 0xf;
- Error *local_err = NULL;
int64_t value;
- visit_type_int(v, name, &value, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
+ if (!visit_type_int(v, name, &value, errp)) {
return;
}
if (value < min || value > max) {
CPUX86State *env = &cpu->env;
const int64_t min = 0;
const int64_t max = 0xff;
- Error *local_err = NULL;
int64_t value;
- visit_type_int(v, name, &value, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
+ if (!visit_type_int(v, name, &value, errp)) {
return;
}
if (value < min || value > max) {
CPUX86State *env = &cpu->env;
const int64_t min = 0;
const int64_t max = 0xf;
- Error *local_err = NULL;
int64_t value;
- visit_type_int(v, name, &value, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
+ if (!visit_type_int(v, name, &value, errp)) {
return;
}
if (value < min || value > max) {
X86CPU *cpu = X86_CPU(obj);
const int64_t min = 0;
const int64_t max = INT64_MAX;
- Error *local_err = NULL;
int64_t value;
- visit_type_int(v, name, &value, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
+ if (!visit_type_int(v, name, &value, errp)) {
return;
}
if (value < min || value > max) {
if (!pv->value) {
continue;
}
- object_property_parse(OBJECT(cpu), pv->value, pv->prop,
+ object_property_parse(OBJECT(cpu), pv->prop, pv->value,
&error_abort);
}
}
PropValue *p;
for (p = vdef->props; p && p->prop; p++) {
- object_property_parse(OBJECT(cpu), p->value, p->prop,
+ object_property_parse(OBJECT(cpu), p->prop, p->value,
&error_abort);
}
*/
/* CPU models only set _minimum_ values for level/xlevel: */
- object_property_set_uint(OBJECT(cpu), def->level, "min-level",
+ object_property_set_uint(OBJECT(cpu), "min-level", def->level,
&error_abort);
- object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel",
+ object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
&error_abort);
- object_property_set_int(OBJECT(cpu), def->family, "family",
- &error_abort);
- object_property_set_int(OBJECT(cpu), def->model, "model",
- &error_abort);
- object_property_set_int(OBJECT(cpu), def->stepping, "stepping",
+ object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
+ object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
+ object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
&error_abort);
- object_property_set_str(OBJECT(cpu), def->model_id, "model-id",
+ object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
&error_abort);
for (w = 0; w < FEATURE_WORDS; w++) {
env->features[w] = def->features[w];
vendor = host_vendor;
}
- object_property_set_str(OBJECT(cpu), vendor, "vendor",
- &error_abort);
+ object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
x86_cpu_apply_version_props(cpu, model);
}
Error *err = NULL;
for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
- object_property_set_qobject(obj, qdict_entry_value(prop),
- qdict_entry_key(prop), &err);
- if (err) {
+ if (!object_property_set_qobject(obj, qdict_entry_key(prop),
+ qdict_entry_value(prop), &err)) {
break;
}
}
*ebx |= (cs->nr_cores * cs->nr_threads) << 16;
*edx |= CPUID_HT;
}
+ if (!cpu->enable_pmu) {
+ *ecx &= ~CPUID_EXT_PDCM;
+ }
break;
case 2:
/* cache info: needed for Pentium Pro compatibility */
*eax = cpu->phys_bits;
}
*ebx = env->features[FEAT_8000_0008_EBX];
- *ecx = 0;
- *edx = 0;
if (cs->nr_cores * cs->nr_threads > 1) {
- *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
+ /*
+ * Bits 15:12 is "The number of bits in the initial
+ * Core::X86::Apic::ApicId[ApicId] value that indicate
+ * thread ID within a package". This is already stored at
+ * CPUX86State::pkg_offset.
+ * Bits 7:0 is "The number of threads in the package is NC+1"
+ */
+ *ecx = (env->pkg_offset << 12) |
+ ((cs->nr_cores * cs->nr_threads) - 1);
+ } else {
+ *ecx = 0;
}
+ *edx = 0;
break;
case 0x8000000A:
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
if (cpu->apic_state == NULL) {
return;
}
- object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
- errp);
+ qdev_realize(DEVICE(cpu->apic_state), NULL, errp);
/* Map APIC MMIO area */
apic = APIC_COMMON(cpu->apic_state);
if (smram) {
cpu->smram = g_new(MemoryRegion, 1);
memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
- smram, 0, 1ull << 32);
+ smram, 0, 4 * GiB);
memory_region_set_enabled(cpu->smram, true);
memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
}
for (l = plus_features; l; l = l->next) {
const char *prop = l->data;
- object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
- if (local_err) {
+ if (!object_property_set_bool(OBJECT(cpu), prop, true, &local_err)) {
goto out;
}
}
for (l = minus_features; l; l = l->next) {
const char *prop = l->data;
- object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
- if (local_err) {
+ if (!object_property_set_bool(OBJECT(cpu), prop, false, &local_err)) {
goto out;
}
}
DeviceState *dev = DEVICE(obj);
X86CPU *cpu = X86_CPU(obj);
BitProperty *fp = opaque;
- Error *local_err = NULL;
bool value;
if (dev->realized) {
return;
}
- visit_type_bool(v, name, &value, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
+ if (!visit_type_bool(v, name, &value, errp)) {
return;
}
x86_cpu_register_bit_prop(cpu, name, w, bitnr);
}
+#if !defined(CONFIG_USER_ONLY)
static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
errp);
qapi_free_GuestPanicInformation(panic_info);
}
+#endif /* !CONFIG_USER_ONLY */
static void x86_cpu_initfn(Object *obj)
{
x86_cpu_get_unavailable_features,
NULL, NULL, NULL);
+#if !defined(CONFIG_USER_ONLY)
object_property_add(obj, "crash-information", "GuestPanicInformation",
x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
+#endif
for (w = 0; w < FEATURE_WORDS; w++) {
int bitnr;
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
#endif
cc->dump_state = x86_cpu_dump_state;
- cc->get_crash_info = x86_cpu_get_crash_info;
cc->set_pc = x86_cpu_set_pc;
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
+ cc->get_crash_info = x86_cpu_get_crash_info;
cc->write_elf64_note = x86_cpu_write_elf64_note;
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;