int i;
#define DEFO32(name, offset) \
- QREG_##name = tcg_global_mem_new_i32(cpu_env, \
+ QREG_##name = tcg_global_mem_new_i32(tcg_env, \
offsetof(CPUM68KState, offset), #name);
#define DEFO64(name, offset) \
- QREG_##name = tcg_global_mem_new_i64(cpu_env, \
+ QREG_##name = tcg_global_mem_new_i64(tcg_env, \
offsetof(CPUM68KState, offset), #name);
#include "qregs.h.inc"
#undef DEFO32
#undef DEFO64
- cpu_halted = tcg_global_mem_new_i32(cpu_env,
+ cpu_halted = tcg_global_mem_new_i32(tcg_env,
-offsetof(M68kCPU, env) +
offsetof(CPUState, halted), "HALTED");
- cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
+ cpu_exception_index = tcg_global_mem_new_i32(tcg_env,
-offsetof(M68kCPU, env) +
offsetof(CPUState, exception_index),
"EXCEPTION");
p = cpu_reg_names;
for (i = 0; i < 8; i++) {
sprintf(p, "D%d", i);
- cpu_dregs[i] = tcg_global_mem_new(cpu_env,
+ cpu_dregs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUM68KState, dregs[i]), p);
p += 3;
sprintf(p, "A%d", i);
- cpu_aregs[i] = tcg_global_mem_new(cpu_env,
+ cpu_aregs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUM68KState, aregs[i]), p);
p += 3;
}
for (i = 0; i < 4; i++) {
sprintf(p, "ACC%d", i);
- cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_macc[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUM68KState, macc[i]), p);
p += 5;
}
- NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
- store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
+ NULL_QREG = tcg_global_mem_new(tcg_env, -4, "NULL");
+ store_dummy = tcg_global_mem_new(tcg_env, -8, "NULL");
}
/* internal defines */
static void gen_raise_exception(int nr)
{
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(nr));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(nr));
}
static void gen_raise_exception_format2(DisasContext *s, int nr,
* Re-use mmu.ar for the purpose, since that's only valid
* after tlb_fill.
*/
- tcg_gen_st_i32(tcg_constant_i32(this_pc), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(this_pc), tcg_env,
offsetof(CPUM68KState, mmu.ar));
gen_raise_exception(nr);
s->base.is_jmp = DISAS_NORETURN;
{
switch (opsize) {
case OS_BYTE:
- if (sign) {
- tcg_gen_ext8s_i32(res, val);
- } else {
- tcg_gen_ext8u_i32(res, val);
- }
- break;
case OS_WORD:
- if (sign) {
- tcg_gen_ext16s_i32(res, val);
- } else {
- tcg_gen_ext16u_i32(res, val);
- }
- break;
case OS_LONG:
- tcg_gen_mov_i32(res, val);
+ tcg_gen_ext_i32(res, val, opsize | (sign ? MO_SIGN : 0));
break;
default:
g_assert_not_reached();
break;
case CC_OP_DYNAMIC:
- gen_helper_flush_flags(cpu_env, QREG_CC_OP);
+ gen_helper_flush_flags(tcg_env, QREG_CC_OP);
s->cc_op_synced = 1;
break;
default:
- gen_helper_flush_flags(cpu_env, tcg_constant_i32(s->cc_op));
+ gen_helper_flush_flags(tcg_env, tcg_constant_i32(s->cc_op));
s->cc_op_synced = 1;
break;
}
reg = get_areg(s, reg0);
result = gen_ldst(s, opsize, reg, val, what, index);
if (what == EA_STORE || !addrp) {
- TCGv tmp = tcg_temp_new();
+ tmp = tcg_temp_new();
if (reg0 == 7 && opsize == OS_BYTE &&
m68k_feature(s->env, M68K_FEATURE_M68K)) {
tcg_gen_addi_i32(tmp, reg, 2);
static TCGv_ptr gen_fp_ptr(int freg)
{
TCGv_ptr fp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
+ tcg_gen_addi_ptr(fp, tcg_env, offsetof(CPUM68KState, fregs[freg]));
return fp;
}
static TCGv_ptr gen_fp_result_ptr(void)
{
TCGv_ptr fp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
+ tcg_gen_addi_ptr(fp, tcg_env, offsetof(CPUM68KState, fp_result));
return fp;
}
case OS_WORD:
case OS_LONG:
tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE);
- gen_helper_exts32(cpu_env, fp, tmp);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_SINGLE:
tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
- gen_helper_extf32(cpu_env, fp, tmp);
+ gen_helper_extf32(tcg_env, fp, tmp);
break;
case OS_DOUBLE:
tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ);
- gen_helper_extf64(cpu_env, fp, t64);
+ gen_helper_extf64(tcg_env, fp, t64);
break;
case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
case OS_BYTE:
case OS_WORD:
case OS_LONG:
- gen_helper_reds32(tmp, cpu_env, fp);
+ gen_helper_reds32(tmp, tcg_env, fp);
tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE);
break;
case OS_SINGLE:
- gen_helper_redf32(tmp, cpu_env, fp);
+ gen_helper_redf32(tmp, tcg_env, fp);
tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
break;
case OS_DOUBLE:
- gen_helper_redf64(t64, cpu_env, fp);
+ gen_helper_redf64(t64, tcg_env, fp);
tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ);
break;
case OS_EXTENDED:
case OS_BYTE:
case OS_WORD:
case OS_LONG:
- gen_helper_reds32(reg, cpu_env, fp);
+ gen_helper_reds32(reg, tcg_env, fp);
break;
case OS_SINGLE:
- gen_helper_redf32(reg, cpu_env, fp);
+ gen_helper_redf32(reg, tcg_env, fp);
break;
default:
g_assert_not_reached();
tmp = tcg_temp_new();
switch (opsize) {
case OS_BYTE:
- tcg_gen_ext8s_i32(tmp, reg);
- gen_helper_exts32(cpu_env, fp, tmp);
- break;
case OS_WORD:
- tcg_gen_ext16s_i32(tmp, reg);
- gen_helper_exts32(cpu_env, fp, tmp);
- break;
case OS_LONG:
- gen_helper_exts32(cpu_env, fp, reg);
+ tcg_gen_ext_i32(tmp, reg, opsize | MO_SIGN);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_SINGLE:
- gen_helper_extf32(cpu_env, fp, reg);
+ gen_helper_extf32(tcg_env, fp, reg);
break;
default:
g_assert_not_reached();
switch (opsize) {
case OS_BYTE:
tmp = tcg_constant_i32((int8_t)read_im8(env, s));
- gen_helper_exts32(cpu_env, fp, tmp);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_WORD:
tmp = tcg_constant_i32((int16_t)read_im16(env, s));
- gen_helper_exts32(cpu_env, fp, tmp);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_LONG:
tmp = tcg_constant_i32(read_im32(env, s));
- gen_helper_exts32(cpu_env, fp, tmp);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_SINGLE:
tmp = tcg_constant_i32(read_im32(env, s));
- gen_helper_extf32(cpu_env, fp, tmp);
+ gen_helper_extf32(tcg_env, fp, tmp);
break;
case OS_DOUBLE:
t64 = tcg_constant_i64(read_im64(env, s));
- gen_helper_extf64(cpu_env, fp, t64);
+ gen_helper_extf64(tcg_env, fp, t64);
break;
case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
destr = tcg_constant_i32(REG(insn, 9));
ilen = tcg_constant_i32(s->pc - s->base.pc_next);
if (sign) {
- gen_helper_divsw(cpu_env, destr, src, ilen);
+ gen_helper_divsw(tcg_env, destr, src, ilen);
} else {
- gen_helper_divuw(cpu_env, destr, src, ilen);
+ gen_helper_divuw(tcg_env, destr, src, ilen);
}
set_cc_op(s, CC_OP_FLAGS);
reg = tcg_constant_i32(REG(ext, 0));
ilen = tcg_constant_i32(s->pc - s->base.pc_next);
if (sign) {
- gen_helper_divsll(cpu_env, num, reg, den, ilen);
+ gen_helper_divsll(tcg_env, num, reg, den, ilen);
} else {
- gen_helper_divull(cpu_env, num, reg, den, ilen);
+ gen_helper_divull(tcg_env, num, reg, den, ilen);
}
set_cc_op(s, CC_OP_FLAGS);
return;
reg = tcg_constant_i32(REG(ext, 0));
ilen = tcg_constant_i32(s->pc - s->base.pc_next);
if (sign) {
- gen_helper_divsl(cpu_env, num, reg, den, ilen);
+ gen_helper_divsl(tcg_env, num, reg, den, ilen);
} else {
- gen_helper_divul(cpu_env, num, reg, den, ilen);
+ gen_helper_divul(tcg_env, num, reg, den, ilen);
}
set_cc_op(s, CC_OP_FLAGS);
update_cc_op(s);
dest = tcg_temp_new();
- gen_helper_get_ccr(dest, cpu_env);
+ gen_helper_get_ccr(dest, tcg_env);
return dest;
}
} else {
/* Must writeback before changing security state. */
do_writebacks(s);
- gen_helper_set_sr(cpu_env, tcg_constant_i32(val));
+ gen_helper_set_sr(tcg_env, tcg_constant_i32(val));
}
set_cc_op(s, CC_OP_FLAGS);
}
static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
{
if (ccr_only) {
- gen_helper_set_ccr(cpu_env, val);
+ gen_helper_set_ccr(tcg_env, val);
} else {
/* Must writeback before changing security state. */
do_writebacks(s);
- gen_helper_set_sr(cpu_env, val);
+ gen_helper_set_sr(tcg_env, val);
}
set_cc_op(s, CC_OP_FLAGS);
}
*/
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
- gen_helper_exit_atomic(cpu_env);
+ gen_helper_exit_atomic(tcg_env);
} else {
TCGv regs = tcg_constant_i32(REG(ext2, 6) |
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
- gen_helper_cas2w(cpu_env, regs, addr1, addr2);
+ gen_helper_cas2w(tcg_env, regs, addr1, addr2);
}
/* Note that cas2w also assigned to env->cc_op. */
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
- gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
+ gen_helper_cas2l_parallel(tcg_env, regs, addr1, addr2);
} else {
- gen_helper_cas2l(cpu_env, regs, addr1, addr2);
+ gen_helper_cas2l(tcg_env, regs, addr1, addr2);
}
/* Note that cas2l also assigned to env->cc_op. */
return;
}
- gen_helper_reset(cpu_env);
+ gen_helper_reset(tcg_env);
}
#endif
}
if (is_sign) {
- gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
+ gen_helper_bfexts_mem(dest, tcg_env, addr, ofs, len);
tcg_gen_mov_i32(QREG_CC_N, dest);
} else {
TCGv_i64 tmp = tcg_temp_new_i64();
- gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
+ gen_helper_bfextu_mem(tmp, tcg_env, addr, ofs, len);
tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
}
set_cc_op(s, CC_OP_LOGIC);
switch (insn & 0x0f00) {
case 0x0a00: /* bfchg */
- gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ gen_helper_bfchg_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break;
case 0x0c00: /* bfclr */
- gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ gen_helper_bfclr_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break;
case 0x0d00: /* bfffo */
t64 = tcg_temp_new_i64();
- gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
+ gen_helper_bfffo_mem(t64, tcg_env, addr, ofs, len);
tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
break;
case 0x0e00: /* bfset */
- gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ gen_helper_bfset_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break;
case 0x0800: /* bftst */
- gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ gen_helper_bfexts_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break;
default:
g_assert_not_reached();
ofs = tcg_constant_i32(extract32(ext, 6, 5));
}
- gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
+ gen_helper_bfins_mem(QREG_CC_N, tcg_env, addr, src, ofs, len);
set_cc_op(s, CC_OP_LOGIC);
}
reg = gen_extend(s, DREG(insn, 9), opsize, 1);
gen_flush_flags(s);
- gen_helper_chk(cpu_env, reg, src);
+ gen_helper_chk(tcg_env, reg, src);
}
DISAS_INSN(chk2)
}
gen_flush_flags(s);
- gen_helper_chk2(cpu_env, reg, bound1, bound2);
+ gen_helper_chk2(tcg_env, reg, bound1, bound2);
}
static void m68k_copy_line(TCGv dst, TCGv src, int index)
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
- tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
+ tcg_gen_ld_i32(AREG(insn, 0), tcg_env,
offsetof(CPUM68KState, sp[M68K_USP]));
}
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
- tcg_gen_st_i32(AREG(insn, 0), cpu_env,
+ tcg_gen_st_i32(AREG(insn, 0), tcg_env,
offsetof(CPUM68KState, sp[M68K_USP]));
}
} else {
reg = DREG(ext, 12);
}
- gen_helper_cf_movec_to(cpu_env, tcg_constant_i32(ext & 0xfff), reg);
+ gen_helper_cf_movec_to(tcg_env, tcg_constant_i32(ext & 0xfff), reg);
gen_exit_tb(s);
}
}
creg = tcg_constant_i32(ext & 0xfff);
if (insn & 1) {
- gen_helper_m68k_movec_to(cpu_env, creg, reg);
+ gen_helper_m68k_movec_to(tcg_env, creg, reg);
} else {
- gen_helper_m68k_movec_from(reg, cpu_env, creg);
+ gen_helper_m68k_movec_from(reg, tcg_env, creg);
}
gen_exit_tb(s);
}
}
opmode = tcg_constant_i32((insn >> 3) & 3);
- gen_helper_pflush(cpu_env, AREG(insn, 0), opmode);
+ gen_helper_pflush(tcg_env, AREG(insn, 0), opmode);
}
DISAS_INSN(ptest)
return;
}
is_read = tcg_constant_i32((insn >> 5) & 1);
- gen_helper_ptest(cpu_env, AREG(insn, 0), is_read);
+ gen_helper_ptest(tcg_env, AREG(insn, 0), is_read);
}
#endif
tcg_gen_movi_i32(res, 0);
break;
case M68K_FPSR:
- tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
+ tcg_gen_ld_i32(res, tcg_env, offsetof(CPUM68KState, fpsr));
break;
case M68K_FPCR:
- tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
+ tcg_gen_ld_i32(res, tcg_env, offsetof(CPUM68KState, fpcr));
break;
}
}
case M68K_FPIAR:
break;
case M68K_FPSR:
- tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
+ tcg_gen_st_i32(val, tcg_env, offsetof(CPUM68KState, fpsr));
break;
case M68K_FPCR:
- gen_helper_set_fpcr(cpu_env, val);
+ gen_helper_set_fpcr(tcg_env, val);
break;
}
}
* only available to store register to memory
*/
if (opsize == OS_EXTENDED) {
- gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemx_st_predec(tmp, tcg_env, addr, tmp);
} else {
- gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemd_st_predec(tmp, tcg_env, addr, tmp);
}
} else {
/* postincrement addressing mode */
if (opsize == OS_EXTENDED) {
if (is_load) {
- gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemx_ld_postinc(tmp, tcg_env, addr, tmp);
} else {
- gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemx_st_postinc(tmp, tcg_env, addr, tmp);
}
} else {
if (is_load) {
- gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemd_ld_postinc(tmp, tcg_env, addr, tmp);
} else {
- gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemd_st_postinc(tmp, tcg_env, addr, tmp);
}
}
}
/* fmovecr */
TCGv rom_offset = tcg_constant_i32(opmode);
cpu_dest = gen_fp_ptr(REG(ext, 7));
- gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
+ gen_helper_fconst(tcg_env, cpu_dest, rom_offset);
return;
}
break;
EA_STORE, IS_USER(s)) == -1) {
gen_addr_fault(s);
}
- gen_helper_ftst(cpu_env, cpu_src);
+ gen_helper_ftst(tcg_env, cpu_src);
return;
case 4: /* fmove to control register. */
case 5: /* fmove from control register. */
gen_fp_move(cpu_dest, cpu_src);
break;
case 0x40: /* fsmove */
- gen_helper_fsround(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsround(tcg_env, cpu_dest, cpu_src);
break;
case 0x44: /* fdmove */
- gen_helper_fdround(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fdround(tcg_env, cpu_dest, cpu_src);
break;
case 1: /* fint */
- gen_helper_firound(cpu_env, cpu_dest, cpu_src);
+ gen_helper_firound(tcg_env, cpu_dest, cpu_src);
break;
case 2: /* fsinh */
- gen_helper_fsinh(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsinh(tcg_env, cpu_dest, cpu_src);
break;
case 3: /* fintrz */
- gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fitrunc(tcg_env, cpu_dest, cpu_src);
break;
case 4: /* fsqrt */
- gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsqrt(tcg_env, cpu_dest, cpu_src);
break;
case 0x41: /* fssqrt */
- gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fssqrt(tcg_env, cpu_dest, cpu_src);
break;
case 0x45: /* fdsqrt */
- gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fdsqrt(tcg_env, cpu_dest, cpu_src);
break;
case 0x06: /* flognp1 */
- gen_helper_flognp1(cpu_env, cpu_dest, cpu_src);
+ gen_helper_flognp1(tcg_env, cpu_dest, cpu_src);
break;
case 0x08: /* fetoxm1 */
- gen_helper_fetoxm1(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fetoxm1(tcg_env, cpu_dest, cpu_src);
break;
case 0x09: /* ftanh */
- gen_helper_ftanh(cpu_env, cpu_dest, cpu_src);
+ gen_helper_ftanh(tcg_env, cpu_dest, cpu_src);
break;
case 0x0a: /* fatan */
- gen_helper_fatan(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fatan(tcg_env, cpu_dest, cpu_src);
break;
case 0x0c: /* fasin */
- gen_helper_fasin(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fasin(tcg_env, cpu_dest, cpu_src);
break;
case 0x0d: /* fatanh */
- gen_helper_fatanh(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fatanh(tcg_env, cpu_dest, cpu_src);
break;
case 0x0e: /* fsin */
- gen_helper_fsin(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsin(tcg_env, cpu_dest, cpu_src);
break;
case 0x0f: /* ftan */
- gen_helper_ftan(cpu_env, cpu_dest, cpu_src);
+ gen_helper_ftan(tcg_env, cpu_dest, cpu_src);
break;
case 0x10: /* fetox */
- gen_helper_fetox(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fetox(tcg_env, cpu_dest, cpu_src);
break;
case 0x11: /* ftwotox */
- gen_helper_ftwotox(cpu_env, cpu_dest, cpu_src);
+ gen_helper_ftwotox(tcg_env, cpu_dest, cpu_src);
break;
case 0x12: /* ftentox */
- gen_helper_ftentox(cpu_env, cpu_dest, cpu_src);
+ gen_helper_ftentox(tcg_env, cpu_dest, cpu_src);
break;
case 0x14: /* flogn */
- gen_helper_flogn(cpu_env, cpu_dest, cpu_src);
+ gen_helper_flogn(tcg_env, cpu_dest, cpu_src);
break;
case 0x15: /* flog10 */
- gen_helper_flog10(cpu_env, cpu_dest, cpu_src);
+ gen_helper_flog10(tcg_env, cpu_dest, cpu_src);
break;
case 0x16: /* flog2 */
- gen_helper_flog2(cpu_env, cpu_dest, cpu_src);
+ gen_helper_flog2(tcg_env, cpu_dest, cpu_src);
break;
case 0x18: /* fabs */
- gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fabs(tcg_env, cpu_dest, cpu_src);
break;
case 0x58: /* fsabs */
- gen_helper_fsabs(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsabs(tcg_env, cpu_dest, cpu_src);
break;
case 0x5c: /* fdabs */
- gen_helper_fdabs(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fdabs(tcg_env, cpu_dest, cpu_src);
break;
case 0x19: /* fcosh */
- gen_helper_fcosh(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fcosh(tcg_env, cpu_dest, cpu_src);
break;
case 0x1a: /* fneg */
- gen_helper_fneg(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fneg(tcg_env, cpu_dest, cpu_src);
break;
case 0x5a: /* fsneg */
- gen_helper_fsneg(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsneg(tcg_env, cpu_dest, cpu_src);
break;
case 0x5e: /* fdneg */
- gen_helper_fdneg(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fdneg(tcg_env, cpu_dest, cpu_src);
break;
case 0x1c: /* facos */
- gen_helper_facos(cpu_env, cpu_dest, cpu_src);
+ gen_helper_facos(tcg_env, cpu_dest, cpu_src);
break;
case 0x1d: /* fcos */
- gen_helper_fcos(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fcos(tcg_env, cpu_dest, cpu_src);
break;
case 0x1e: /* fgetexp */
- gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fgetexp(tcg_env, cpu_dest, cpu_src);
break;
case 0x1f: /* fgetman */
- gen_helper_fgetman(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fgetman(tcg_env, cpu_dest, cpu_src);
break;
case 0x20: /* fdiv */
- gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fdiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x60: /* fsdiv */
- gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsdiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x64: /* fddiv */
- gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fddiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x21: /* fmod */
- gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fmod(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x22: /* fadd */
- gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fadd(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x62: /* fsadd */
- gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsadd(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x66: /* fdadd */
- gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fdadd(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x23: /* fmul */
- gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x63: /* fsmul */
- gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x67: /* fdmul */
- gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fdmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x24: /* fsgldiv */
- gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsgldiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x25: /* frem */
- gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_frem(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x26: /* fscale */
- gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fscale(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x27: /* fsglmul */
- gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsglmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x28: /* fsub */
- gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsub(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x68: /* fssub */
- gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fssub(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x6c: /* fdsub */
- gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fdsub(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x30: case 0x31: case 0x32:
case 0x33: case 0x34: case 0x35:
case 0x36: case 0x37: {
TCGv_ptr cpu_dest2 = gen_fp_ptr(REG(ext, 0));
- gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src);
+ gen_helper_fsincos(tcg_env, cpu_dest, cpu_dest2, cpu_src);
}
break;
case 0x38: /* fcmp */
- gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
+ gen_helper_fcmp(tcg_env, cpu_src, cpu_dest);
return;
case 0x3a: /* ftst */
- gen_helper_ftst(cpu_env, cpu_src);
+ gen_helper_ftst(tcg_env, cpu_src);
return;
default:
goto undef;
}
- gen_helper_ftst(cpu_env, cpu_dest);
+ gen_helper_ftst(tcg_env, cpu_dest);
return;
undef:
/* FIXME: Is this right for offset addressing modes? */
ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
}
if (s->env->macsr & MACSR_FI) {
- gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
+ gen_helper_macmulf(s->mactmp, tcg_env, rx, ry);
} else {
if (s->env->macsr & MACSR_SU)
- gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
+ gen_helper_macmuls(s->mactmp, tcg_env, rx, ry);
else
- gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
+ gen_helper_macmulu(s->mactmp, tcg_env, rx, ry);
switch ((ext >> 9) & 3) {
case 1:
tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
if (s->env->macsr & MACSR_FI)
- gen_helper_macsatf(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsatf(tcg_env, tcg_constant_i32(acc));
else if (s->env->macsr & MACSR_SU)
- gen_helper_macsats(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsats(tcg_env, tcg_constant_i32(acc));
else
- gen_helper_macsatu(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsatu(tcg_env, tcg_constant_i32(acc));
#if 0
/* Disabled because conditional branches clobber temporary vars. */
else
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
if (s->env->macsr & MACSR_FI)
- gen_helper_macsatf(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsatf(tcg_env, tcg_constant_i32(acc));
else if (s->env->macsr & MACSR_SU)
- gen_helper_macsats(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsats(tcg_env, tcg_constant_i32(acc));
else
- gen_helper_macsatu(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsatu(tcg_env, tcg_constant_i32(acc));
#if 0
/* Disabled because conditional branches clobber temporary vars. */
if (l1 != -1)
gen_set_label(l1);
#endif
}
- gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(acc));
+ gen_helper_mac_set_flags(tcg_env, tcg_constant_i32(acc));
if (insn & 0x30) {
TCGv rw;
accnum = (insn >> 9) & 3;
acc = MACREG(accnum);
if (s->env->macsr & MACSR_FI) {
- gen_helper_get_macf(rx, cpu_env, acc);
+ gen_helper_get_macf(rx, tcg_env, acc);
} else if ((s->env->macsr & MACSR_OMC) == 0) {
tcg_gen_extrl_i64_i32(rx, acc);
} else if (s->env->macsr & MACSR_SU) {
TCGv dest;
src = insn & 3;
dest = tcg_constant_i32((insn >> 9) & 3);
- gen_helper_mac_move(cpu_env, dest, tcg_constant_i32(src));
+ gen_helper_mac_move(tcg_env, dest, tcg_constant_i32(src));
gen_mac_clear_flags();
- gen_helper_mac_set_flags(cpu_env, dest);
+ gen_helper_mac_set_flags(tcg_env, dest);
}
DISAS_INSN(from_macsr)
reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI)
- gen_helper_get_mac_extf(reg, cpu_env, acc);
+ gen_helper_get_mac_extf(reg, tcg_env, acc);
else
- gen_helper_get_mac_exti(reg, cpu_env, acc);
+ gen_helper_get_mac_exti(reg, tcg_env, acc);
}
DISAS_INSN(macsr_to_ccr)
/* Note that X and C are always cleared. */
tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V);
- gen_helper_set_ccr(cpu_env, tmp);
+ gen_helper_set_ccr(tcg_env, tmp);
set_cc_op(s, CC_OP_FLAGS);
}
}
tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
gen_mac_clear_flags();
- gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(accnum));
+ gen_helper_mac_set_flags(tcg_env, tcg_constant_i32(accnum));
}
DISAS_INSN(to_macsr)
{
TCGv val;
SRC_EA(env, val, OS_LONG, 0, NULL);
- gen_helper_set_macsr(cpu_env, val);
+ gen_helper_set_macsr(tcg_env, val);
gen_exit_tb(s);
}
SRC_EA(env, val, OS_LONG, 0, NULL);
acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI)
- gen_helper_set_mac_extf(cpu_env, val, acc);
+ gen_helper_set_mac_extf(tcg_env, val, acc);
else if (s->env->macsr & MACSR_SU)
- gen_helper_set_mac_exts(cpu_env, val, acc);
+ gen_helper_set_mac_exts(tcg_env, val, acc);
else
- gen_helper_set_mac_extu(cpu_env, val, acc);
+ gen_helper_set_mac_extu(tcg_env, val, acc);
}
static disas_proc opcode_table[65536];
static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUM68KState *env = cpu->env_ptr;
+ CPUM68KState *env = cpu_env(cpu);
dc->env = env;
dc->pc = dc->base.pc_first;
static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUM68KState *env = cpu->env_ptr;
+ CPUM68KState *env = cpu_env(cpu);
uint16_t insn = read_im16(env, dc);
opcode_table[insn](env, dc, insn);
projects / mirror_qemu.git / blobdiff