static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
- CPUState *cs = CPU(mb_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
struct microblaze_mmu *mmu = &env->mmu;
unsigned int tlb_size;
uint32_t tlb_tag, end, t;
lu->vaddr = tlb_tag;
lu->paddr = tlb_rpn & mmu->c_addr_mask;
- lu->paddr = tlb_rpn;
lu->size = tlb_size;
lu->err = ERR_HIT;
lu->idx = i;
void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
uint64_t tmp64;
unsigned int i;
qemu_log_mask(CPU_LOG_MMU,
/* Changes to the zone protection reg flush the QEMU TLB.
Fortunately, these are very uncommon. */
if (v != env->mmu.regs[rn]) {
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
env->mmu.regs[rn] = v;
break;