#include "exec/exec-all.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-clock.h"
-#include "hw/semihosting/semihost.h"
+#include "semihosting/semihost.h"
#include "qapi/qapi-commands-machine-target.h"
+#include "fpu_helper.h"
-static void mips_cpu_set_pc(CPUState *cs, vaddr value)
+const char regnames[32][4] = {
+ "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+ "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+ "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
+};
+
+static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64)
+{
+ if (is_fpu64) {
+ qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n",
+ fpr->w[FP_ENDIAN_IDX], fpr->d,
+ (double)fpr->fd,
+ (double)fpr->fs[FP_ENDIAN_IDX],
+ (double)fpr->fs[!FP_ENDIAN_IDX]);
+ } else {
+ fpr_t tmp;
+
+ tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX];
+ tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX];
+ qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n",
+ tmp.w[FP_ENDIAN_IDX], tmp.d,
+ (double)tmp.fd,
+ (double)tmp.fs[FP_ENDIAN_IDX],
+ (double)tmp.fs[!FP_ENDIAN_IDX]);
+ }
+}
+
+static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
+{
+ int i;
+ bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
+
+ qemu_fprintf(f,
+ "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
+ env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
+ get_float_exception_flags(&env->active_fpu.fp_status));
+ for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
+ qemu_fprintf(f, "%3s: ", fregnames[i]);
+ fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64);
+ }
+}
+
+static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
MIPSCPU *cpu = MIPS_CPU(cs);
CPUMIPSState *env = &cpu->env;
+ int i;
- env->active_tc.PC = value & ~(target_ulong)1;
- if (value & 1) {
- env->hflags |= MIPS_HFLAG_M16;
- } else {
- env->hflags &= ~(MIPS_HFLAG_M16);
+ qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
+ " LO=0x" TARGET_FMT_lx " ds %04x "
+ TARGET_FMT_lx " " TARGET_FMT_ld "\n",
+ env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
+ env->hflags, env->btarget, env->bcond);
+ for (i = 0; i < 32; i++) {
+ if ((i & 3) == 0) {
+ qemu_fprintf(f, "GPR%02d:", i);
+ }
+ qemu_fprintf(f, " %s " TARGET_FMT_lx,
+ regnames[i], env->active_tc.gpr[i]);
+ if ((i & 3) == 3) {
+ qemu_fprintf(f, "\n");
+ }
+ }
+
+ qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
+ TARGET_FMT_lx "\n",
+ env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
+ qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
+ PRIx64 "\n",
+ env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
+ qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
+ env->CP0_Config2, env->CP0_Config3);
+ qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
+ env->CP0_Config4, env->CP0_Config5);
+ if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
+ fpu_dump_state(env, f, flags);
}
}
-static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+ MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
+ vp->env.exception_base = address;
+}
+
+static void mips_cpu_set_pc(CPUState *cs, vaddr value)
{
MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
- env->active_tc.PC = tb->pc;
- env->hflags &= ~MIPS_HFLAG_BMASK;
- env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
+ mips_env_set_pc(&cpu->env, value);
}
static bool mips_cpu_has_work(CPUState *cs)
if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
if (cpu_mips_hw_interrupts_enabled(env) ||
- (env->insn_flags & ISA_MIPS32R6)) {
+ (env->insn_flags & ISA_MIPS_R6)) {
has_work = true;
}
}
return has_work;
}
-#include "translate_init.c.inc"
+#include "cpu-defs.c.inc"
-/* TODO QOM'ify CPU reset and remove */
-static void cpu_state_reset(CPUMIPSState *env)
+static void mips_cpu_reset(DeviceState *dev)
{
- CPUState *cs = env_cpu(env);
+ CPUState *cs = CPU(dev);
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
+ CPUMIPSState *env = &cpu->env;
+
+ mcc->parent_reset(dev);
+
+ memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;
/* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
#endif /* !CONFIG_USER_ONLY */
- if ((env->insn_flags & ISA_MIPS32R6) &&
+ if ((env->insn_flags & ISA_MIPS_R6) &&
(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
/* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
env->CP0_Status |= (1 << CP0St_FR);
}
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
/* PTW = 1 */
env->CP0_PWSize = 0x40;
/* GDI = 12 */
env->hflags |= MIPS_HFLAG_M16;
}
- /* MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
- msa_reset(env);
- }
+ msa_reset(env);
compute_hflags(env);
restore_fp_status(env);
/* UHI interface can be used to obtain argc and argv */
env->active_tc.gpr[4] = -1;
}
-}
-
-static void mips_cpu_reset(DeviceState *dev)
-{
- CPUState *s = CPU(dev);
- MIPSCPU *cpu = MIPS_CPU(s);
- MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
- CPUMIPSState *env = &cpu->env;
-
- mcc->parent_reset(dev);
-
- memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
-
- cpu_state_reset(env);
#ifndef CONFIG_USER_ONLY
if (kvm_enabled()) {
{
CPUMIPSState *env = &cpu->env;
- env->cp0_count_ns = cpu->cp0_count_rate
- * clock_get_ns(MIPS_CPU(cpu)->clock);
+ env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
+ cpu->cp0_count_rate);
assert(env->cp0_count_ns);
}
env->exception_base = (int32_t)0xBFC00000;
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
mmu_init(env, env->cpu_model);
#endif
fpu_init(env, env->cpu_model);
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
cpu_set_cpustate_pointers(cpu);
- cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu);
+ cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
env->cpu_model = mcc->cpu_def;
}
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps mips_sysemu_ops = {
+};
+#endif
+
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+/*
+ * NB: cannot be const, as some elements are changed for specific
+ * mips hardware (see hw/mips/jazz.c).
+ */
+static struct TCGCPUOps mips_tcg_ops = {
+ .initialize = mips_tcg_init,
+ .synchronize_from_tb = mips_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = mips_cpu_exec_interrupt,
+ .tlb_fill = mips_cpu_tlb_fill,
+
+#if !defined(CONFIG_USER_ONLY)
+ .do_interrupt = mips_cpu_do_interrupt,
+ .do_transaction_failed = mips_cpu_do_transaction_failed,
+ .do_unaligned_access = mips_cpu_do_unaligned_access,
+ .io_recompile_replay_branch = mips_io_recompile_replay_branch,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void mips_cpu_class_init(ObjectClass *c, void *data)
{
MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
- cc->do_interrupt = mips_cpu_do_interrupt;
- cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
- cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mips_cpu_do_transaction_failed;
- cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_mips_cpu;
+ cc->legacy_vmsd = &vmstate_mips_cpu;
+ cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
-#ifdef CONFIG_TCG
- cc->tcg_initialize = mips_tcg_init;
- cc->tlb_fill = mips_cpu_tlb_fill;
-#endif
-
cc->gdb_num_core_regs = 73;
cc->gdb_stop_before_watchpoint = true;
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &mips_tcg_ops;
+#endif /* CONFIG_TCG */
}
static const TypeInfo mips_cpu_type_info = {
{
ObjectClass *oc = data;
CpuDefinitionInfoList **cpu_list = user_data;
- CpuDefinitionInfoList *entry;
CpuDefinitionInfo *info;
const char *typename;
strlen(typename) - strlen("-" TYPE_MIPS_CPU));
info->q_typename = g_strdup(typename);
- entry = g_malloc0(sizeof(*entry));
- entry->value = info;
- entry->next = *cpu_list;
- *cpu_list = entry;
+ QAPI_LIST_PREPEND(*cpu_list, info);
}
CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
}
-
-void cpu_set_exception_base(int vp_index, target_ulong address)
-{
- MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
- vp->env.exception_base = address;
-}
projects / mirror_qemu.git / blobdiff