Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into staging

[mirror_qemu.git] / target / mips / internal.h

diff --git a/target/mips/internal.h b/target/mips/internal.h
index ac6e03e2f259a69c52b2a9aa4afd2c2651ccdf95..57b312689a6427fb654ff957772767161acc7ae1 100644 (file)
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -47,6 +47,15 @@ struct mips_def_t {
     target_ulong CP0_LLAddr_rw_bitmask;
     int CP0_LLAddr_shift;
     int32_t SYNCI_Step;
+    /*
+     * @CCRes: rate at which the coprocessor 0 counter increments
+     *
+     * The Count register acts as a timer, incrementing at a constant rate,
+     * whether or not an instruction is executed, retired, or any forward
+     * progress is made through the pipeline. The rate at which the counter
+     * increments is implementation dependent, and is a function of the
+     * pipeline clock of the processor, not the issue width of the processor.
+     */
     int32_t CCRes;
     int32_t CP0_Status_rw_bitmask;
     int32_t CP0_TCStatus_rw_bitmask;