R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
};
-/* Multiplication variants of the vr54xx. */
-#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
-
-enum {
- OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
- OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
- OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
- OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
- OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
- OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
- OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
- OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
- OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
- OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
- OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
- OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
- OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
- OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
-};
-
/* REGIMM (rt field) opcodes */
#define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
#include "exec/gen-icount.h"
-#define gen_helper_0e0i(name, arg) do { \
- TCGv_i32 helper_tmp = tcg_const_i32(arg); \
- gen_helper_##name(cpu_env, helper_tmp); \
- tcg_temp_free_i32(helper_tmp); \
- } while (0)
-
-#define gen_helper_0e1i(name, arg1, arg2) do { \
- TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
- gen_helper_##name(cpu_env, arg1, helper_tmp); \
- tcg_temp_free_i32(helper_tmp); \
- } while (0)
-
-#define gen_helper_1e0i(name, ret, arg1) do { \
- TCGv_i32 helper_tmp = tcg_const_i32(arg1); \
- gen_helper_##name(ret, cpu_env, helper_tmp); \
- tcg_temp_free_i32(helper_tmp); \
- } while (0)
-
-#define gen_helper_1e1i(name, ret, arg1, arg2) do { \
- TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
- gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \
- tcg_temp_free_i32(helper_tmp); \
- } while (0)
-
-#define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
- TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
- gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \
- tcg_temp_free_i32(helper_tmp); \
- } while (0)
-
-#define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \
- TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
- gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \
- tcg_temp_free_i32(helper_tmp); \
- } while (0)
-
-#define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \
- TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
- gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \
- tcg_temp_free_i32(helper_tmp); \
- } while (0)
-
#define DISAS_STOP DISAS_TARGET_0
#define DISAS_EXIT DISAS_TARGET_1
void generate_exception_err(DisasContext *ctx, int excp, int err)
{
- TCGv_i32 texcp = tcg_const_i32(excp);
- TCGv_i32 terr = tcg_const_i32(err);
save_cpu_state(ctx, 1);
- gen_helper_raise_exception_err(cpu_env, texcp, terr);
- tcg_temp_free_i32(terr);
- tcg_temp_free_i32(texcp);
+ gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(excp),
+ tcg_constant_i32(err));
ctx->base.is_jmp = DISAS_NORETURN;
}
void generate_exception(DisasContext *ctx, int excp)
{
- gen_helper_0e0i(raise_exception, excp);
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
}
void generate_exception_end(DisasContext *ctx, int excp)
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
DisasContext *ctx) \
{ \
- gen_helper_1e1i(insn, ret, arg1, mem_idx); \
+ gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \
}
#endif
OP_LD_ATOMIC(ll, ld32s);
*/
tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 7);
-#ifndef TARGET_WORDS_BIGENDIAN
- tcg_gen_xori_tl(t1, t1, 7);
-#endif
+ if (!cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, 7);
+ }
tcg_gen_shli_tl(t1, t1, 3);
tcg_gen_andi_tl(t0, t0, ~7);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ);
*/
tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 7);
-#ifdef TARGET_WORDS_BIGENDIAN
- tcg_gen_xori_tl(t1, t1, 7);
-#endif
+ if (cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, 7);
+ }
tcg_gen_shli_tl(t1, t1, 3);
tcg_gen_andi_tl(t0, t0, ~7);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ);
*/
tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 3);
-#ifndef TARGET_WORDS_BIGENDIAN
- tcg_gen_xori_tl(t1, t1, 3);
-#endif
+ if (!cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, 3);
+ }
tcg_gen_shli_tl(t1, t1, 3);
tcg_gen_andi_tl(t0, t0, ~3);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
*/
tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 3);
-#ifdef TARGET_WORDS_BIGENDIAN
- tcg_gen_xori_tl(t1, t1, 3);
-#endif
+ if (cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, 3);
+ }
tcg_gen_shli_tl(t1, t1, 3);
tcg_gen_andi_tl(t0, t0, ~3);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
tcg_temp_free(t1);
}
-static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
- int rd, int rs, int rt)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
-
- gen_load_gpr(t0, rs);
- gen_load_gpr(t1, rt);
-
- switch (opc) {
- case OPC_VR54XX_MULS:
- gen_helper_muls(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSU:
- gen_helper_mulsu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MACC:
- gen_helper_macc(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MACCU:
- gen_helper_maccu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MSAC:
- gen_helper_msac(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MSACU:
- gen_helper_msacu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULHI:
- gen_helper_mulhi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULHIU:
- gen_helper_mulhiu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSHI:
- gen_helper_mulshi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSHIU:
- gen_helper_mulshiu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MACCHI:
- gen_helper_macchi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MACCHIU:
- gen_helper_macchiu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MSACHI:
- gen_helper_msachi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MSACHIU:
- gen_helper_msachiu(t0, cpu_env, t0, t1);
- break;
- default:
- MIPS_INVAL("mul vr54xx");
- gen_reserved_instruction(ctx);
- goto out;
- }
- gen_store_gpr(t0, rd);
-
- out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
static void gen_cl(DisasContext *ctx, uint32_t opc,
int rd, int rs)
{
t1 = tcg_temp_new();
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 3);
-#ifndef TARGET_WORDS_BIGENDIAN
- tcg_gen_xori_tl(t1, t1, 3);
-#endif
+ if (!cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, 3);
+ }
tcg_gen_shli_tl(t1, t1, 3);
tcg_gen_andi_tl(t0, t0, ~3);
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
t1 = tcg_temp_new();
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 3);
-#ifdef TARGET_WORDS_BIGENDIAN
- tcg_gen_xori_tl(t1, t1, 3);
-#endif
+ if (cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, 3);
+ }
tcg_gen_shli_tl(t1, t1, 3);
tcg_gen_andi_tl(t0, t0, ~3);
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
t1 = tcg_temp_new();
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 7);
-#ifndef TARGET_WORDS_BIGENDIAN
- tcg_gen_xori_tl(t1, t1, 7);
-#endif
+ if (!cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, 7);
+ }
tcg_gen_shli_tl(t1, t1, 3);
tcg_gen_andi_tl(t0, t0, ~7);
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
t1 = tcg_temp_new();
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 7);
-#ifdef TARGET_WORDS_BIGENDIAN
- tcg_gen_xori_tl(t1, t1, 7);
-#endif
+ if (cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, 7);
+ }
tcg_gen_shli_tl(t1, t1, 3);
tcg_gen_andi_tl(t0, t0, ~7);
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
break;
#endif
case OPC_GSLWXC1:
- check_cp1_enabled(ctx);
gen_base_offset_addr(ctx, t0, rs, offset);
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
break;
#if defined(TARGET_MIPS64)
case OPC_GSLDXC1:
- check_cp1_enabled(ctx);
gen_base_offset_addr(ctx, t0, rs, offset);
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
gen_save_pc(dest);
- if (ctx->base.singlestep_enabled) {
- save_cpu_state(ctx, 0);
- gen_helper_raise_exception_debug(cpu_env);
- } else {
- tcg_gen_lookup_and_goto_ptr();
- }
+ tcg_gen_lookup_and_goto_ptr();
}
}
break;
case 3:
/* XXX: For now we support only a single FPU context. */
- {
- TCGv_i32 fs_tmp = tcg_const_i32(rd);
-
- gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
- tcg_temp_free_i32(fs_tmp);
- }
+ gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt);
/* Stop translation as we may have changed hflags */
ctx->base.is_jmp = DISAS_STOP;
break;
case OPC_CTC1:
gen_load_gpr(t0, rt);
save_cpu_state(ctx, 0);
- {
- TCGv_i32 fs_tmp = tcg_const_i32(fs);
-
- gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
- tcg_temp_free_i32(fs_tmp);
- }
+ gen_helper_0e2i(ctc1, t0, tcg_constant_i32(fs), rt);
/* Stop translation as we may have changed hflags */
ctx->base.is_jmp = DISAS_STOP;
break;
gen_set_label(l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
tcg_temp_free(t0);
-#ifdef TARGET_WORDS_BIGENDIAN
- gen_load_fpr32(ctx, fp, fs);
- gen_load_fpr32h(ctx, fph, ft);
- gen_store_fpr32h(ctx, fp, fd);
- gen_store_fpr32(ctx, fph, fd);
-#else
- gen_load_fpr32h(ctx, fph, fs);
- gen_load_fpr32(ctx, fp, ft);
- gen_store_fpr32(ctx, fph, fd);
- gen_store_fpr32h(ctx, fp, fd);
-#endif
+ if (cpu_is_bigendian(ctx)) {
+ gen_load_fpr32(ctx, fp, fs);
+ gen_load_fpr32h(ctx, fph, ft);
+ gen_store_fpr32h(ctx, fp, fd);
+ gen_store_fpr32(ctx, fph, fd);
+ } else {
+ gen_load_fpr32h(ctx, fph, fs);
+ gen_load_fpr32(ctx, fp, ft);
+ gen_store_fpr32(ctx, fph, fd);
+ gen_store_fpr32h(ctx, fp, fd);
+ }
gen_set_label(l2);
tcg_temp_free_i32(fp);
tcg_temp_free_i32(fph);
} else {
tcg_gen_mov_tl(cpu_PC, btarget);
}
- if (ctx->base.singlestep_enabled) {
- save_cpu_state(ctx, 0);
- gen_helper_raise_exception_debug(cpu_env);
- }
tcg_gen_lookup_and_goto_ptr();
break;
default:
} else {
/* OPC_JIC, OPC_JIALC */
TCGv tbase = tcg_temp_new();
- TCGv toffset = tcg_temp_new();
+ TCGv toffset = tcg_constant_tl(offset);
gen_load_gpr(tbase, rt);
- tcg_gen_movi_tl(toffset, offset);
gen_op_addr_add(ctx, btarget, tbase, toffset);
tcg_temp_free(tbase);
- tcg_temp_free(toffset);
}
break;
default:
TCGv t0;
TCGv t1;
TCGv v1_t;
- TCGv v2_t;
int16_t imm;
if ((ret == 0) && (check_ret == 1)) {
t0 = tcg_temp_new();
t1 = tcg_temp_new();
v1_t = tcg_temp_new();
- v2_t = tcg_temp_new();
gen_load_gpr(v1_t, v1);
- gen_load_gpr(v2_t, v2);
switch (op1) {
case OPC_EXTR_W_DSP:
break;
case OPC_DEXTRV_S_H:
tcg_gen_movi_tl(t0, v2);
- tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
break;
case OPC_DEXTRV_L:
tcg_gen_movi_tl(t0, v2);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(v1_t);
- tcg_temp_free(v2_t);
}
/* End MIPSDSP functions. */
static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
{
- int rs, rt, rd, sa;
+ int rs, rt, rd;
uint32_t op1;
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
- sa = (ctx->opcode >> 6) & 0x1f;
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
break;
case OPC_MULT:
case OPC_MULTU:
- if (sa) {
- check_insn(ctx, INSN_VR54XX);
- op1 = MASK_MUL_VR54XX(ctx->opcode);
- gen_mul_vr54xx(ctx, op1, rd, rs, rt);
- } else {
- gen_muldiv(ctx, op1, rd & 3, rs, rt);
- }
+ gen_muldiv(ctx, op1, rd & 3, rs, rt);
break;
case OPC_DIV:
case OPC_DIVU:
break;
#endif
case OPC_JR:
- gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
+ gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4);
break;
case OPC_SPIM:
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("PMON / selsl");
gen_reserved_instruction(ctx);
#else
- gen_helper_0e0i(pmon, sa);
+ gen_helper_pmon(cpu_env, tcg_constant_i32(sa));
#endif
break;
case OPC_SYSCALL:
/* Treat as NOP. */
break;
case OPC_PREF:
- if (ctx->insn_flags & INSN_R5900) {
- /* Treat as NOP. */
- } else {
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
- /* Treat as NOP. */
- }
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900);
+ /* Treat as NOP. */
break;
/* Floating point (COP1). */
/* Transition to the auto-generated decoder. */
+ /* Vendor specific extensions */
+ if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) {
+ return;
+ }
+ if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
+ return;
+ }
+
/* ISA extensions */
if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
return;
if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) {
return;
}
- if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) {
- return;
- }
if (decode_opc_legacy(env, ctx)) {
return;
ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
ctx->saved_pc = -1;
ctx->insn_flags = env->insn_flags;
+ ctx->CP0_Config0 = env->CP0_Config0;
ctx->CP0_Config1 = env->CP0_Config1;
ctx->CP0_Config2 = env->CP0_Config2;
ctx->CP0_Config3 = env->CP0_Config3;
ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
+ /*
+ * Execute a branch and its delay slot as a single instruction.
+ * This is what GDB expects and is consistent with what the
+ * hardware does (e.g. if a delay slot instruction faults, the
+ * reported PC is the PC of the branch).
+ */
+ if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) {
+ ctx->base.max_insns = 2;
+ }
+
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
ctx->hflags);
}
ctx->btarget);
}
-static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
- const CPUBreakpoint *bp)
-{
- DisasContext *ctx = container_of(dcbase, DisasContext, base);
-
- save_cpu_state(ctx, 1);
- ctx->base.is_jmp = DISAS_NORETURN;
- gen_helper_raise_exception_debug(cpu_env);
- /*
- * The address covered by the breakpoint must be included in
- * [tb->pc, tb->pc + tb->size) in order to for it to be
- * properly cleared -- thus we increment the PC here so that
- * the logic setting tb->size below does the right thing.
- */
- ctx->base.pc_next += 4;
- return true;
-}
-
static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
CPUMIPSState *env = cs->env_ptr;
is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
if (ctx->insn_flags & ISA_NANOMIPS32) {
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
insn_bytes = decode_isa_nanomips(env, ctx);
} else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
- ctx->opcode = translator_ldl(env, ctx->base.pc_next);
+ ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
insn_bytes = 4;
decode_opc(env, ctx);
} else if (ctx->insn_flags & ASE_MICROMIPS) {
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
insn_bytes = decode_isa_micromips(env, ctx);
} else if (ctx->insn_flags & ASE_MIPS16) {
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
insn_bytes = decode_ase_mips16e(env, ctx);
} else {
gen_reserved_instruction(ctx);
if (ctx->base.is_jmp != DISAS_NEXT) {
return;
}
+
/*
- * Execute a branch and its delay slot as a single instruction.
- * This is what GDB expects and is consistent with what the
- * hardware does (e.g. if a delay slot instruction faults, the
- * reported PC is the PC of the branch).
+ * End the TB on (most) page crossings.
+ * See mips_tr_init_disas_context about single-stepping a branch
+ * together with its delay slot.
*/
- if (ctx->base.singlestep_enabled &&
- (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
- ctx->base.is_jmp = DISAS_TOO_MANY;
- }
- if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
+ if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
+ && !ctx->base.singlestep_enabled) {
ctx->base.is_jmp = DISAS_TOO_MANY;
}
}
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
- save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
- gen_helper_raise_exception_debug(cpu_env);
- } else {
- switch (ctx->base.is_jmp) {
- case DISAS_STOP:
- gen_save_pc(ctx->base.pc_next);
- tcg_gen_lookup_and_goto_ptr();
- break;
- case DISAS_NEXT:
- case DISAS_TOO_MANY:
- save_cpu_state(ctx, 0);
- gen_goto_tb(ctx, 0, ctx->base.pc_next);
- break;
- case DISAS_EXIT:
- tcg_gen_exit_tb(NULL, 0);
- break;
- case DISAS_NORETURN:
- break;
- default:
- g_assert_not_reached();
- }
+ switch (ctx->base.is_jmp) {
+ case DISAS_STOP:
+ gen_save_pc(ctx->base.pc_next);
+ tcg_gen_lookup_and_goto_ptr();
+ break;
+ case DISAS_NEXT:
+ case DISAS_TOO_MANY:
+ save_cpu_state(ctx, 0);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
+ break;
+ case DISAS_EXIT:
+ tcg_gen_exit_tb(NULL, 0);
+ break;
+ case DISAS_NORETURN:
+ break;
+ default:
+ g_assert_not_reached();
}
}
.init_disas_context = mips_tr_init_disas_context,
.tb_start = mips_tr_tb_start,
.insn_start = mips_tr_insn_start,
- .breakpoint_check = mips_tr_breakpoint_check,
.translate_insn = mips_tr_translate_insn,
.tb_stop = mips_tr_tb_stop,
.disas_log = mips_tr_disas_log,
projects / mirror_qemu.git / blobdiff