#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "qemu/error-report.h"
+#include "qemu/qemu-print.h"
#include "sysemu/hw_accel.h"
#include "kvm_ppc.h"
#include "mmu-hash64.h"
#include "hw/hw.h"
#include "mmu-book3s-v3.h"
-//#define DEBUG_SLB
+/* #define DEBUG_SLB */
#ifdef DEBUG_SLB
# define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
LOG_SLB("%s: slot %d %016" PRIx64 " %016"
PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
- /* We check for 1T matches on all MMUs here - if the MMU
+ /*
+ * We check for 1T matches on all MMUs here - if the MMU
* doesn't have 1T segment support, we will have prevented 1T
- * entries from being inserted in the slbmte code. */
+ * entries from being inserted in the slbmte code.
+ */
if (((slb->esid == esid_256M) &&
((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
|| ((slb->esid == esid_1T) &&
return NULL;
}
-void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
+void dump_slb(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
int i;
cpu_synchronize_state(CPU(cpu));
- cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
+ qemu_printf("SLB\tESID\t\t\tVSID\n");
for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
slbe = env->slb[i].esid;
slbv = env->slb[i].vsid;
if (slbe == 0 && slbv == 0) {
continue;
}
- cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
+ qemu_printf("%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
i, slbe, slbv);
}
}
void helper_slbia(CPUPPCState *env)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
int n;
/* XXX: Warning: slbia never invalidates the first segment */
if (slb->esid & SLB_ESID_V) {
slb->esid &= ~SLB_ESID_V;
- /* XXX: given the fact that segment size is 256 MB or 1TB,
+ /*
+ * XXX: given the fact that segment size is 256 MB or 1TB,
* and we still don't have a tlb_flush_mask(env, n, mask)
* in QEMU, we just invalidate all TLBs
*/
static void __helper_slbie(CPUPPCState *env, target_ulong addr,
target_ulong global)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
ppc_slb_t *slb;
slb = slb_lookup(cpu, addr);
if (slb->esid & SLB_ESID_V) {
slb->esid &= ~SLB_ESID_V;
- /* XXX: given the fact that segment size is 256 MB or 1TB,
+ /*
+ * XXX: given the fact that segment size is 256 MB or 1TB,
* and we still don't have a tlb_flush_mask(env, n, mask)
* in QEMU, we just invalidate all TLBs
*/
void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
{
CPUPPCState *env = &cpu->env;
unsigned pp, key;
- /* Some pp bit combinations have undefined behaviour, so default
- * to no access in those cases */
+ /*
+ * Some pp bit combinations have undefined behaviour, so default
+ * to no access in those cases
+ */
int prot = 0;
key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
}
key = HPTE64_R_KEY(pte.pte1);
- amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
+ amrbits = (env->spr[SPR_AMR] >> 2 * (31 - key)) & 0x3;
/* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
/* env->spr[SPR_AMR]); */
if (*pshift == 0) {
continue;
}
- /* We don't do anything with pshift yet as qemu TLB only deals
- * with 4K pages anyway
+ /*
+ * We don't do anything with pshift yet as qemu TLB only
+ * deals with 4K pages anyway
*/
pte->pte0 = pte0;
pte->pte1 = pte1;
uint64_t vsid, epnmask, epn, ptem;
const PPCHash64SegmentPageSizes *sps = slb->sps;
- /* The SLB store path should prevent any bad page size encodings
- * getting in there, so: */
+ /*
+ * The SLB store path should prevent any bad page size encodings
+ * getting in there, so:
+ */
assert(sps);
/* If ISL is set in LPCR we need to clamp the page size to 4K */
}
+static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
+{
+ hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 16;
+
+ if (cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->hpte_set_r(cpu->vhyp, ptex, pte1);
+ return;
+ }
+ base = ppc_hash64_hpt_base(cpu);
+
+
+ /* The HW performs a non-atomic byte update */
+ stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
+}
+
+static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
+{
+ hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 15;
+
+ if (cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->hpte_set_c(cpu->vhyp, ptex, pte1);
+ return;
+ }
+ base = ppc_hash64_hpt_base(cpu);
+
+ /* The HW performs a non-atomic byte update */
+ stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
+}
+
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
int rwx, int mmu_idx)
{
hwaddr ptex;
ppc_hash_pte64_t pte;
int exec_prot, pp_prot, amr_prot, prot;
- uint64_t new_pte1;
const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
hwaddr raddr;
assert((rwx == 0) || (rwx == 1) || (rwx == 2));
- /* Note on LPCR usage: 970 uses HID4, but our special variant
- * of store_spr copies relevant fields into env->spr[SPR_LPCR].
- * Similarily we filter unimplemented bits when storing into
- * LPCR depending on the MMU version. This code can thus just
- * use the LPCR "as-is".
+ /*
+ * Note on LPCR usage: 970 uses HID4, but our special variant of
+ * store_spr copies relevant fields into env->spr[SPR_LPCR].
+ * Similarily we filter unimplemented bits when storing into LPCR
+ * depending on the MMU version. This code can thus just use the
+ * LPCR "as-is".
*/
/* 1. Handle real mode accesses */
if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
- /* Translation is supposedly "off" */
- /* In real mode the top 4 effective address bits are (mostly) ignored */
+ /*
+ * Translation is supposedly "off", but in real mode the top 4
+ * effective address bits are (mostly) ignored
+ */
raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
/* In HV mode, add HRMOR if top EA bit is clear */
/* 6. Update PTE referenced and changed bits if necessary */
- new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
- if (rwx == 1) {
- new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
- } else {
- /* Treat the page as read-only for now, so that a later write
- * will pass through this function again to set the C bit */
- prot &= ~PAGE_WRITE;
+ if (!(pte.pte1 & HPTE64_R_R)) {
+ ppc_hash64_set_r(cpu, ptex, pte.pte1);
}
-
- if (new_pte1 != pte.pte1) {
- ppc_hash64_store_hpte(cpu, ptex, pte.pte0, new_pte1);
+ if (!(pte.pte1 & HPTE64_R_C)) {
+ if (rwx == 1) {
+ ppc_hash64_set_c(cpu, ptex, pte.pte1);
+ } else {
+ /*
+ * Treat the page as read-only for now, so that a later write
+ * will pass through this function again to set the C bit
+ */
+ prot &= ~PAGE_WRITE;
+ }
}
/* 7. Determine the real address from the PTE */
& TARGET_PAGE_MASK;
}
-void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
- uint64_t pte0, uint64_t pte1)
-{
- hwaddr base;
- hwaddr offset = ptex * HASH_PTE_SIZE_64;
-
- if (cpu->vhyp) {
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- vhc->store_hpte(cpu->vhyp, ptex, pte0, pte1);
- return;
- }
- base = ppc_hash64_hpt_base(cpu);
-
- stq_phys(CPU(cpu)->as, base + offset, pte0);
- stq_phys(CPU(cpu)->as, base + offset + HASH_PTE_SIZE_64 / 2, pte1);
-}
-
void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
target_ulong pte0, target_ulong pte1)
{
return;
}
- /* Make one up. Mostly ignore the ESID which will not be
- * needed for translation
+ /*
+ * Make one up. Mostly ignore the ESID which will not be needed
+ * for translation
*/
vsid = SLB_VSID_VRMA;
vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
}
env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26;
- /* XXX We could also write LPID from HID4 here
+ /*
+ * XXX We could also write LPID from HID4 here
* but since we don't tag any translation on it
* it doesn't actually matter
- */
- /* XXX For proper emulation of 970 we also need
+ *
+ * XXX For proper emulation of 970 we also need
* to dig HRMOR out of HID5
*/
break;
case POWERPC_MMU_3_00: /* P9 */
lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
(LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
- LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR |
+ LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
(LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
void helper_store_lpcr(CPUPPCState *env, target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
ppc_store_lpcr(cpu, val);
}