#include "time_helper.h"
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
+#include "exec/tb-flush.h"
#include "sysemu/cpu-timers.h"
#include "qemu/guest-random.h"
#include "qapi/error.h"
csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
}
+/* Predicates */
+#if !defined(CONFIG_USER_ONLY)
+RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
+{
+ bool virt = env->virt_enabled;
+
+ if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) {
+ return RISCV_EXCP_NONE;
+ }
+
+ if (!(env->mstateen[index] & bit)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ if (virt) {
+ if (!(env->hstateen[index] & bit)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+
+ if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ }
+
+ if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
+ if (!(env->sstateen[index] & bit)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ }
+
+ return RISCV_EXCP_NONE;
+}
+#endif
+
static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env) &&
- !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+ !riscv_cpu_cfg(env)->ext_zfinx) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
static RISCVException vs(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (cpu->cfg.ext_zve32f) {
+ if (riscv_cpu_cfg(env)->ext_zve32f) {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
return RISCV_EXCP_ILLEGAL_INST;
}
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (!get_field(env->hcounteren, ctr_mask) ||
(env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
return ctr(env, csrno);
}
+static RISCVException zcmt(CPURISCVState *env, int csrno)
+{
+ if (!riscv_cpu_cfg(env)->ext_zcmt) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+#if !defined(CONFIG_USER_ONLY)
+ RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+#endif
+
+ return RISCV_EXCP_NONE;
+}
+
#if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
+ int pmu_num = riscv_cpu_cfg(env)->pmu_num;
int ctr_index;
int base_csrno = CSR_MHPMCOUNTER3;
base_csrno += 0x80;
}
ctr_index = csrno - base_csrno;
- if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
- /* The PMU is not enabled or counter is out of range*/
+ if (!pmu_num || ctr_index >= pmu_num) {
+ /* The PMU is not enabled or counter is out of range */
return RISCV_EXCP_ILLEGAL_INST;
}
static RISCVException sscofpmf(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_sscofpmf) {
+ if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
return RISCV_EXCP_ILLEGAL_INST;
}
static int aia_any(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_smaia) {
+ if (!riscv_cpu_cfg(env)->ext_smaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
static int aia_any32(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_smaia) {
+ if (!riscv_cpu_cfg(env)->ext_smaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
static int aia_smode(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
static int aia_smode32(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
static RISCVException mstateen(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_smstateen) {
+ if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_smstateen) {
+ if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
static RISCVException sstateen(CPURISCVState *env, int csrno)
{
- bool virt = riscv_cpu_virt_enabled(env);
+ bool virt = env->virt_enabled;
int index = csrno - CSR_SSTATEEN0;
- RISCVCPU *cpu = env_archcpu(env);
- if (!cpu->cfg.ext_smstateen) {
+ if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
static RISCVException sstc(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
bool hmode_check = false;
- if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
+ if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_ILLEGAL_INST;
}
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
get_field(env->henvcfg, HENVCFG_STCE))) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
return sstc(env, csrno);
}
+static RISCVException satp(CPURISCVState *env, int csrno)
+{
+ if (env->priv == PRV_S && !env->virt_enabled &&
+ get_field(env->mstatus, MSTATUS_TVM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (env->priv == PRV_S && env->virt_enabled &&
+ get_field(env->hstatus, HSTATUS_VTVM)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+
+ return smode(env, csrno);
+}
+
+static RISCVException hgatp(CPURISCVState *env, int csrno)
+{
+ if (env->priv == PRV_S && !env->virt_enabled &&
+ get_field(env->mstatus, MSTATUS_TVM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return hmode(env, csrno);
+}
+
/* Checks if PointerMasking registers could be accessed */
static RISCVException pointer_masking(CPURISCVState *env, int csrno)
{
static int aia_hmode(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
static int aia_hmode32(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
static RISCVException seed(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_zkr) {
+ if (!riscv_cpu_cfg(env)->ext_zkr) {
return RISCV_EXCP_ILLEGAL_INST;
}
*/
if (env->priv == PRV_M) {
return RISCV_EXCP_NONE;
- } else if (riscv_cpu_virt_enabled(env)) {
+ } else if (env->virt_enabled) {
if (env->mseccfg & MSECCFG_SSEED) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
} else {
static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
{
- *val = env_archcpu(env)->cfg.vlen >> 3;
+ *val = riscv_cpu_cfg(env)->vlen >> 3;
return RISCV_EXCP_NONE;
}
* The vstart CSR is defined to have only enough writable bits
* to hold the largest element index, i.e. lg2(VLEN) bits.
*/
- env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
+ env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen));
return RISCV_EXCP_NONE;
}
counter.mhpmcounter_val;
if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
- /**
+ /*
* Counter should not increment if inhibit bit is set. We can't really
* stop the icount counting. Just return the counter value written by
* the supervisor to indicate that counter was not incremented.
}
}
- /**
+ /*
* The kernel computes the perf delta by subtracting the current value from
* the value it initialized previously (ctr_val).
*/
static RISCVException read_time(CPURISCVState *env, int csrno,
target_ulong *val)
{
- uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
+ uint64_t delta = env->virt_enabled ? env->htimedelta : 0;
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
static RISCVException read_timeh(CPURISCVState *env, int csrno,
target_ulong *val)
{
- uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
+ uint64_t delta = env->virt_enabled ? env->htimedelta : 0;
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
if (riscv_cpu_mxl(env) == MXL_RV32) {
env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
} else {
env->vstimecmp = val;
}
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
return RISCV_EXCP_NONE;
static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val);
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
return RISCV_EXCP_NONE;
static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
target_ulong *val)
{
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
*val = env->vstimecmp;
} else {
*val = env->stimecmp;
static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
target_ulong *val)
{
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
*val = env->vstimecmp >> 32;
} else {
*val = env->stimecmp >> 32;
static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
env->stimecmp = val;
}
- riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
+ riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
return RISCV_EXCP_NONE;
}
static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
}
env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val);
- riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
+ riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
return RISCV_EXCP_NONE;
}
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP |
SIP_LCOFIP;
static const target_ulong hip_writable_mask = MIP_VSSIP;
-static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
+static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
+ MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;
-static const char valid_vm_1_10_32[16] = {
- [VM_1_10_MBARE] = 1,
- [VM_1_10_SV32] = 1
+const bool valid_vm_1_10_32[16] = {
+ [VM_1_10_MBARE] = true,
+ [VM_1_10_SV32] = true
};
-static const char valid_vm_1_10_64[16] = {
- [VM_1_10_MBARE] = 1,
- [VM_1_10_SV39] = 1,
- [VM_1_10_SV48] = 1,
- [VM_1_10_SV57] = 1
+const bool valid_vm_1_10_64[16] = {
+ [VM_1_10_MBARE] = true,
+ [VM_1_10_SV39] = true,
+ [VM_1_10_SV48] = true,
+ [VM_1_10_SV57] = true
};
/* Machine Information Registers */
static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
target_ulong *val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- *val = cpu->cfg.mvendorid;
+ *val = riscv_cpu_cfg(env)->mvendorid;
return RISCV_EXCP_NONE;
}
static RISCVException read_marchid(CPURISCVState *env, int csrno,
target_ulong *val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- *val = cpu->cfg.marchid;
+ *val = riscv_cpu_cfg(env)->marchid;
return RISCV_EXCP_NONE;
}
static RISCVException read_mimpid(CPURISCVState *env, int csrno,
target_ulong *val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- *val = cpu->cfg.mimpid;
+ *val = riscv_cpu_cfg(env)->mimpid;
return RISCV_EXCP_NONE;
}
return RISCV_EXCP_NONE;
}
-static int validate_vm(CPURISCVState *env, target_ulong vm)
+static bool validate_vm(CPURISCVState *env, target_ulong vm)
{
- if (riscv_cpu_mxl(env) == MXL_RV32) {
- return valid_vm_1_10_32[vm & 0xf];
- } else {
- return valid_vm_1_10_64[vm & 0xf];
+ return (vm & 0xf) <=
+ satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
+}
+
+static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
+ target_ulong val)
+{
+ bool valid = false;
+ target_ulong new_mpp = get_field(val, MSTATUS_MPP);
+
+ switch (new_mpp) {
+ case PRV_M:
+ valid = true;
+ break;
+ case PRV_S:
+ valid = riscv_has_ext(env, RVS);
+ break;
+ case PRV_U:
+ valid = riscv_has_ext(env, RVU);
+ break;
}
+
+ /* Remain field unchanged if new_mpp value is invalid */
+ if (!valid) {
+ val = set_field(val, MSTATUS_MPP, old_mpp);
+ }
+
+ return val;
}
static RISCVException write_mstatus(CPURISCVState *env, int csrno,
uint64_t mask = 0;
RISCVMXL xl = riscv_cpu_mxl(env);
+ /*
+ * MPP field have been made WARL since priv version 1.11. However,
+ * legalization for it will not break any software running on 1.10.
+ */
+ val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
+
/* flush tlb on mstatus fields that affect VM */
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
- MSTATUS_MPRV | MSTATUS_SUM)) {
+ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) {
tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
Int128 *val)
{
- *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
+ *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128,
+ env->mstatus));
return RISCV_EXCP_NONE;
}
static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
{
- if (!riscv_cpu_virt_enabled(env)) {
+ if (!env->virt_enabled) {
return csrno;
}
done:
if (ret) {
- return (riscv_cpu_virt_enabled(env) && virt) ?
+ return (env->virt_enabled && virt) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_NONE;
done:
if (ret) {
- return (riscv_cpu_virt_enabled(env) && virt) ?
+ return (env->virt_enabled && virt) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_NONE;
static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+ const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
if (riscv_cpu_mxl(env) == MXL_RV64) {
static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+ const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
(cfg->ext_svadu ? MENVCFG_HADE : 0);
return RISCV_EXCP_NONE;
}
-static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
- uint64_t bit)
-{
- bool virt = riscv_cpu_virt_enabled(env);
- RISCVCPU *cpu = env_archcpu(env);
-
- if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
- return RISCV_EXCP_NONE;
- }
-
- if (!(env->mstateen[index] & bit)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
- if (virt) {
- if (!(env->hstateen[index] & bit)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
-
- if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- }
-
- if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
- if (!(env->sstateen[index] & bit)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- }
-
- return RISCV_EXCP_NONE;
-}
-
static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
target_ulong *val)
{
static RISCVException read_sstateen(CPURISCVState *env, int csrno,
target_ulong *val)
{
- bool virt = riscv_cpu_virt_enabled(env);
+ bool virt = env->virt_enabled;
int index = csrno - CSR_SSTATEEN0;
*val = env->sstateen[index] & env->mstateen[index];
static RISCVException write_sstateen(CPURISCVState *env, int csrno,
uint64_t mask, target_ulong new_val)
{
- bool virt = riscv_cpu_virt_enabled(env);
+ bool virt = env->virt_enabled;
int index = csrno - CSR_SSTATEEN0;
uint64_t wr_mask;
uint64_t *reg;
uint64_t *ret_val,
uint64_t new_val, uint64_t wr_mask)
{
- RISCVCPU *cpu = env_archcpu(env);
uint64_t old_mip, mask = wr_mask & delegable_ints;
uint32_t gin;
new_val |= env->external_seip * MIP_SEIP;
}
- if (cpu->cfg.ext_sstc && (env->priv == PRV_M) &&
+ if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
get_field(env->menvcfg, MENVCFG_STCE)) {
/* sstc extension forbids STIP & VSTIP to be writeable in mip */
mask = mask & ~(MIP_STIP | MIP_VSTIP);
}
if (mask) {
- old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
+ old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask));
} else {
old_mip = env->mip;
}
RISCVException ret;
uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
RISCVException ret;
uint64_t mask = env->mideleg & sip_writable_mask;
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
*val = 0;
return RISCV_EXCP_NONE;
}
-
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return RISCV_EXCP_ILLEGAL_INST;
- } else {
- *val = env->satp;
- }
-
+ *val = env->satp;
return RISCV_EXCP_NONE;
}
static RISCVException write_satp(CPURISCVState *env, int csrno,
target_ulong val)
{
- target_ulong vm, mask;
+ target_ulong mask;
+ bool vm;
if (!riscv_cpu_cfg(env)->mmu) {
return RISCV_EXCP_NONE;
}
if (vm && mask) {
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return RISCV_EXCP_ILLEGAL_INST;
- } else {
- /*
- * The ISA defines SATP.MODE=Bare as "no translation", but we still
- * pass these through QEMU's TLB emulation as it improves
- * performance. Flushing the TLB on SATP writes with paging
- * enabled avoids leaking those invalid cached mappings.
- */
- tlb_flush(env_cpu(env));
- env->satp = val;
- }
+ /*
+ * The ISA defines SATP.MODE=Bare as "no translation", but we still
+ * pass these through QEMU's TLB emulation as it improves
+ * performance. Flushing the TLB on SATP writes with paging
+ * enabled avoids leaking those invalid cached mappings.
+ */
+ tlb_flush(env_cpu(env));
+ env->satp = val;
}
return RISCV_EXCP_NONE;
}
int irq;
uint8_t iprio;
- if (riscv_cpu_virt_enabled(env)) {
+ if (env->virt_enabled) {
return read_vstopi(env, CSR_VSTOPI, val);
}
{
env->hstatus = val;
if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
- qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
+ qemu_log_mask(LOG_UNIMP,
+ "QEMU does not support mixed HSXLEN options.");
}
if (get_field(val, HSTATUS_VSBE) != 0) {
qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
env->hgeie = val;
/* Update mip.SGEIP bit */
- riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
+ riscv_cpu_update_mip(env, MIP_SGEIP,
BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
return RISCV_EXCP_NONE;
}
static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = val;
}
- if (cpu->cfg.ext_sstc && env->rdtime_fn) {
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
}
static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
target_ulong val)
{
- RISCVCPU *cpu = env_archcpu(env);
-
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
- if (cpu->cfg.ext_sstc && env->rdtime_fn) {
- riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
+ riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
}
/* First index has to be a multiple of number of irqs per register */
if (first_index % num_irqs) {
- return (riscv_cpu_virt_enabled(env)) ?
+ return (env->virt_enabled) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
/* First index has to be a multiple of number of irqs per register */
if (first_index % num_irqs) {
- return (riscv_cpu_virt_enabled(env)) ?
+ return (env->virt_enabled) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
target_ulong wpri_val = val & MMTE_MASK;
if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
- "MMTE: WPRI violation written 0x", val,
- "vs expected 0x", wpri_val);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
+ TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x",
+ val, "vs expected 0x", wpri_val);
}
/* for machine mode pm.current is hardwired to 1 */
wpri_val |= MMTE_M_PM_CURRENT;
/* hardwiring pm.instruction bit to 0, since it's not supported yet */
wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
- env->mmte = wpri_val | PM_EXT_DIRTY;
+ env->mmte = wpri_val | EXT_STATUS_DIRTY;
riscv_cpu_update_mask(env);
/* Set XS and SD bits, since PM CSRs are dirty */
target_ulong wpri_val = val & SMTE_MASK;
if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
- "SMTE: WPRI violation written 0x", val,
- "vs expected 0x", wpri_val);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
+ TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x",
+ val, "vs expected 0x", wpri_val);
}
/* if pm.current==0 we can't modify current PM CSRs */
target_ulong wpri_val = val & UMTE_MASK;
if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
- "UMTE: WPRI violation written 0x", val,
- "vs expected 0x", wpri_val);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
+ TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x",
+ val, "vs expected 0x", wpri_val);
}
if (check_pm_current_disabled(env, csrno)) {
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmmask = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmmask = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmmask = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmbase = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmbase = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmbase = val;
}
- env->mmte |= PM_EXT_DIRTY;
+ env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
int csrno,
- bool write_mask,
- RISCVCPU *cpu)
+ bool write_mask)
{
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
bool read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
/* ensure the CSR extension is enabled */
- if (!cpu->cfg.ext_icsr) {
+ if (!riscv_cpu_cfg(env)->ext_icsr) {
return RISCV_EXCP_ILLEGAL_INST;
}
int csr_priv, effective_priv = env->priv;
if (riscv_has_ext(env, RVH) && env->priv == PRV_S &&
- !riscv_cpu_virt_enabled(env)) {
+ !env->virt_enabled) {
/*
* We are in HS mode. Add 1 to the effective privledge level to
* allow us to access the Hypervisor CSRs.
csr_priv = get_field(csrno, 0x300);
if (!env->debugger && (effective_priv < csr_priv)) {
- if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
+ if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
return RISCV_EXCP_ILLEGAL_INST;
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
+ RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
Int128 new_value, Int128 write_mask)
{
RISCVException ret;
- RISCVCPU *cpu = env_archcpu(env);
- ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
+ ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
if (ret != RISCV_EXCP_NONE) {
return ret;
}
* Fall back to 64-bit version for now, if the 128-bit alternative isn't
* at all defined.
* Note, some CSRs don't need to extend to MXLEN (64 upper bits non
- * significant), for those, this fallback is correctly handling the accesses
+ * significant), for those, this fallback is correctly handling the
+ * accesses
*/
target_ulong old_value;
ret = riscv_csrrw_do64(env, csrno, &old_value,
return ret;
}
+static RISCVException read_jvt(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->jvt;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_jvt(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ env->jvt = val;
+ return RISCV_EXCP_NONE;
+}
+
/* Control and Status Register function table */
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */
/* Crypto Extension */
[CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed },
+ /* Zcmt Extension */
+ [CSR_JVT] = {"jvt", zcmt, read_jvt, write_jvt},
+
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
[CSR_MCYCLE] = { "mcycle", any, read_hpmcounter,
/* Supervisor Trap Setup */
[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus,
- NULL, read_sstatus_i128 },
- [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
- [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
+ NULL, read_sstatus_i128 },
+ [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
+ [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren,
- write_scounteren },
+ write_scounteren },
/* Supervisor Trap Handling */
[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch,
.min_priv_ver = PRIV_VERSION_1_12_0 },
/* Supervisor Protection and Translation */
- [CSR_SATP] = { "satp", smode, read_satp, write_satp },
+ [CSR_SATP] = { "satp", satp, read_satp, write_satp },
/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
[CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect },
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HGEIP] = { "hgeip", hmode, read_hgeip,
.min_priv_ver = PRIV_VERSION_1_12_0 },
- [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp,
+ [CSR_HGATP] = { "hgatp", hgatp, read_hgatp, write_hgatp,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
write_htimedelta,
projects / mirror_qemu.git / blobdiff