bool cfg_vta_all_1s;
target_ulong vstart;
bool vl_eq_vlmax;
- uint8_t ntemp;
CPUState *cs;
TCGv zero;
- /* Space for 3 operands plus 1 extra for address computation. */
- TCGv temp[4];
- /* Space for 4 operands(1 dest and <=3 src) for float point computation */
- TCGv_i64 ftemp[4];
- uint8_t nftemp;
/* PointerMasking extension */
bool pm_mask_enabled;
bool pm_base_enabled;
{
return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
- ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
+ ctx->cfg_ptr->ext_xtheadcondmov ||
+ ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv ||
+ ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx ||
ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
}
*/
static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
{
- TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
- TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
+ TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull);
+ TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull);
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
- tcg_temp_free_i64(t_max);
- tcg_temp_free_i64(t_nan);
}
static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
*
* Further, we may provide an extension for word operations.
*/
-static TCGv temp_new(DisasContext *ctx)
-{
- assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
- return ctx->temp[ctx->ntemp++] = tcg_temp_new();
-}
-
static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
{
TCGv t;
case EXT_NONE:
break;
case EXT_SIGN:
- t = temp_new(ctx);
+ t = tcg_temp_new();
tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
return t;
case EXT_ZERO:
- t = temp_new(ctx);
+ t = tcg_temp_new();
tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
return t;
default:
static TCGv dest_gpr(DisasContext *ctx, int reg_num)
{
if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
- return temp_new(ctx);
+ return tcg_temp_new();
}
return cpu_gpr[reg_num];
}
static TCGv dest_gprh(DisasContext *ctx, int reg_num)
{
if (reg_num == 0) {
- return temp_new(ctx);
+ return tcg_temp_new();
}
return cpu_gprh[reg_num];
}
}
}
-static TCGv_i64 ftemp_new(DisasContext *ctx)
-{
- assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp));
- return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64();
-}
-
static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
{
if (!ctx->cfg_ptr->ext_zfinx) {
case MXL_RV32:
#ifdef TARGET_RISCV32
{
- TCGv_i64 t = ftemp_new(ctx);
+ TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]);
return t;
}
switch (get_xl(ctx)) {
case MXL_RV32:
{
- TCGv_i64 t = ftemp_new(ctx);
+ TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
return t;
}
}
if (reg_num == 0) {
- return ftemp_new(ctx);
+ return tcg_temp_new_i64();
}
switch (get_xl(ctx)) {
case MXL_RV32:
- return ftemp_new(ctx);
+ return tcg_temp_new_i64();
#ifdef TARGET_RISCV64
case MXL_RV64:
return cpu_gpr[reg_num];
/* Compute a canonical address from a register plus offset. */
static TCGv get_address(DisasContext *ctx, int rs1, int imm)
{
- TCGv addr = temp_new(ctx);
+ TCGv addr = tcg_temp_new();
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_addi_tl(addr, src1, imm);
return addr;
}
+/* Compute a canonical address from a register plus reg offset. */
+static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
+{
+ TCGv addr = tcg_temp_new();
+ TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
+
+ tcg_gen_add_tl(addr, src1, offs);
+ if (ctx->pm_mask_enabled) {
+ tcg_gen_andc_tl(addr, addr, pm_mask);
+ } else if (get_xl(ctx) == MXL_RV32) {
+ tcg_gen_ext32u_tl(addr, addr);
+ }
+ if (ctx->pm_base_enabled) {
+ tcg_gen_or_tl(addr, addr, pm_base);
+ }
+ return addr;
+}
+
#ifndef CONFIG_USER_ONLY
/* The states of mstatus_fs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- tcg_temp_free(tmp);
}
if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
- tcg_temp_free(tmp);
}
}
#else
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- tcg_temp_free(tmp);
}
if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) {
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
- tcg_temp_free(tmp);
}
}
#else
f128(dest, desth, src1, src1h, ext2);
gen_set_gpr128(ctx, a->rd, dest, desth);
}
- tcg_temp_free(ext2);
return true;
}
#include "insn_trans/trans_rvh.c.inc"
#include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_rvb.c.inc"
+#include "insn_trans/trans_rvzicond.c.inc"
#include "insn_trans/trans_rvzawrs.c.inc"
+#include "insn_trans/trans_rvzicbo.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
ctx->misa_mxl_max = env->misa_mxl_max;
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->cs = cs;
- ctx->ntemp = 0;
- memset(ctx->temp, 0, sizeof(ctx->temp));
- ctx->nftemp = 0;
- memset(ctx->ftemp, 0, sizeof(ctx->ftemp));
ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
+ ctx->virt_inst_excp = false;
}
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cpu->env_ptr;
uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
- int i;
ctx->ol = ctx->xl;
decode_opc(env, ctx, opcode16);
ctx->base.pc_next = ctx->pc_succ_insn;
- for (i = ctx->ntemp - 1; i >= 0; --i) {
- tcg_temp_free(ctx->temp[i]);
- ctx->temp[i] = NULL;
- }
- ctx->ntemp = 0;
- for (i = ctx->nftemp - 1; i >= 0; --i) {
- tcg_temp_free_i64(ctx->ftemp[i]);
- ctx->ftemp[i] = NULL;
- }
- ctx->nftemp = 0;
-
/* Only the first insn within a TB is allowed to cross a page boundary. */
if (ctx->base.is_jmp == DISAS_NEXT) {
if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next);
int len = insn_len(next_insn);
- if (!is_same_page(&ctx->base, ctx->base.pc_next + len)) {
+ if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {
ctx->base.is_jmp = DISAS_TOO_MANY;
}
}
.disas_log = riscv_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
projects / mirror_qemu.git / blobdiff