#include "instmap.h"
#include "internals.h"
+#define HELPER_H "helper.h"
+#include "exec/helper-info.c.inc"
+#undef HELPER_H
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv pm_mask;
static TCGv pm_base;
-#include "exec/gen-icount.h"
-
/*
* If an operation is being performed on less than TARGET_LONG_BITS,
* it may require the inputs to be sign- or zero-extended; which will
typedef struct DisasContext {
DisasContextBase base;
- /* pc_succ_insn points to the instruction following base.pc_next */
- target_ulong pc_succ_insn;
+ target_ulong cur_insn_len;
+ target_ulong pc_save;
target_ulong priv_ver;
RISCVMXL misa_mxl_max;
RISCVMXL xl;
+ RISCVMXL address_xl;
uint32_t misa_ext;
uint32_t opcode;
- uint32_t mstatus_fs;
- uint32_t mstatus_vs;
- uint32_t mstatus_hs_fs;
- uint32_t mstatus_hs_vs;
+ RISCVExtStatus mstatus_fs;
+ RISCVExtStatus mstatus_vs;
uint32_t mem_idx;
- /* Remember the rounding mode encoded in the previous fp instruction,
- which we have already installed into env->fp_status. Or -1 for
- no previous fp instruction. Note that we exit the TB when writing
- to any system register, which includes CSR_FRM, so we do not have
- to reset this known value. */
+ uint32_t priv;
+ /*
+ * Remember the rounding mode encoded in the previous fp instruction,
+ * which we have already installed into env->fp_status. Or -1 for
+ * no previous fp instruction. Note that we exit the TB when writing
+ * to any system register, which includes CSR_FRM, so we do not have
+ * to reset this known value.
+ */
int frm;
RISCVMXL ol;
bool virt_inst_excp;
bool virt_enabled;
const RISCVCPUConfig *cfg_ptr;
- bool hlsx;
/* vector extension */
bool vill;
/*
uint8_t vta;
uint8_t vma;
bool cfg_vta_all_1s;
- target_ulong vstart;
+ bool vstart_eq_zero;
bool vl_eq_vlmax;
CPUState *cs;
TCGv zero;
return ctx->misa_ext & ext;
}
-static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
-{
- return true;
-}
-
-static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
-{
- return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
- ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
- ctx->cfg_ptr->ext_xtheadcondmov ||
- ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv ||
- ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx ||
- ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
-}
-
-#define MATERIALISE_EXT_PREDICATE(ext) \
- static bool has_ ## ext ## _p(DisasContext *ctx) \
- { \
- return ctx->cfg_ptr->ext_ ## ext ; \
- }
-
-MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
-
#ifdef TARGET_RISCV32
#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
#define get_xl(ctx) ((ctx)->xl)
#endif
+#ifdef TARGET_RISCV32
+#define get_address_xl(ctx) MXL_RV32
+#elif defined(CONFIG_USER_ONLY)
+#define get_address_xl(ctx) MXL_RV64
+#else
+#define get_address_xl(ctx) ((ctx)->address_xl)
+#endif
+
/* The word size for this machine mode. */
static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
{
ctx->insn_start = NULL;
}
-static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
+static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
+ target_long diff)
{
- if (get_xl(ctx) == MXL_RV32) {
- dest = (int32_t)dest;
+ target_ulong dest = ctx->base.pc_next + diff;
+
+ assert(ctx->pc_save != -1);
+ if (tb_cflags(ctx->base.tb) & CF_PCREL) {
+ tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save);
+ if (get_xl(ctx) == MXL_RV32) {
+ tcg_gen_ext32s_tl(target, target);
+ }
+ } else {
+ if (get_xl(ctx) == MXL_RV32) {
+ dest = (int32_t)dest;
+ }
+ tcg_gen_movi_tl(target, dest);
}
- tcg_gen_movi_tl(cpu_pc, dest);
}
-static void gen_set_pc(DisasContext *ctx, TCGv dest)
+static void gen_update_pc(DisasContext *ctx, target_long diff)
{
- if (get_xl(ctx) == MXL_RV32) {
- tcg_gen_ext32s_tl(cpu_pc, dest);
- } else {
- tcg_gen_mov_tl(cpu_pc, dest);
- }
+ gen_pc_plus_diff(cpu_pc, ctx, diff);
+ ctx->pc_save = ctx->base.pc_next + diff;
}
static void generate_exception(DisasContext *ctx, int excp)
{
- gen_set_pc_imm(ctx, ctx->base.pc_next);
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
+ gen_update_pc(ctx, 0);
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_exception_illegal(DisasContext *ctx)
{
- tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env,
offsetof(CPURISCVState, bins));
if (ctx->virt_inst_excp) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
}
}
-static void gen_exception_inst_addr_mis(DisasContext *ctx)
+static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target)
{
- tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
+ tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr));
generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
}
{
#ifndef CONFIG_USER_ONLY
if (ctx->itrigger) {
- gen_helper_itrigger_match(cpu_env);
+ gen_helper_itrigger_match(tcg_env);
}
#endif
tcg_gen_lookup_and_goto_ptr();
{
#ifndef CONFIG_USER_ONLY
if (ctx->itrigger) {
- gen_helper_itrigger_match(cpu_env);
+ gen_helper_itrigger_match(tcg_env);
}
#endif
tcg_gen_exit_tb(NULL, 0);
}
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
{
+ target_ulong dest = ctx->base.pc_next + diff;
+
/*
* Under itrigger, instruction executes one by one like singlestep,
* direct block chain benefits will be small.
*/
if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
- tcg_gen_goto_tb(n);
- gen_set_pc_imm(ctx, dest);
+ /*
+ * For pcrel, the pc must always be up-to-date on entry to
+ * the linked TB, so that it can use simple additions for all
+ * further adjustments. For !pcrel, the linked TB is compiled
+ * to know its full virtual address, so we can delay the
+ * update to pc to the unlinked path. A long chain of links
+ * can thus avoid many updates to the PC.
+ */
+ if (tb_cflags(ctx->base.tb) & CF_PCREL) {
+ gen_update_pc(ctx, diff);
+ tcg_gen_goto_tb(n);
+ } else {
+ tcg_gen_goto_tb(n);
+ gen_update_pc(ctx, diff);
+ }
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
- gen_set_pc_imm(ctx, dest);
+ gen_update_pc(ctx, diff);
lookup_and_goto_ptr(ctx);
}
}
}
}
-/* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
+/* assume it is nanboxing (for normal) or sign-extended (for zfinx) */
static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t)
{
if (!ctx->cfg_ptr->ext_zfinx) {
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
- target_ulong next_pc;
+ TCGv succ_pc = dest_gpr(ctx, rd);
/* check misaligned: */
- next_pc = ctx->base.pc_next + imm;
- if (!has_ext(ctx, RVC)) {
- if ((next_pc & 0x3) != 0) {
- gen_exception_inst_addr_mis(ctx);
+ if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
+ if ((imm & 0x3) != 0) {
+ TCGv target_pc = tcg_temp_new();
+ gen_pc_plus_diff(target_pc, ctx, imm);
+ gen_exception_inst_addr_mis(ctx, target_pc);
return;
}
}
- gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
- gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
+ gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
+ gen_set_gpr(ctx, rd, succ_pc);
+
+ gen_goto_tb(ctx, 0, imm); /* must use this for safety */
ctx->base.is_jmp = DISAS_NORETURN;
}
tcg_gen_addi_tl(addr, src1, imm);
if (ctx->pm_mask_enabled) {
tcg_gen_andc_tl(addr, addr, pm_mask);
- } else if (get_xl(ctx) == MXL_RV32) {
+ } else if (get_address_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
if (ctx->pm_base_enabled) {
tcg_gen_or_tl(addr, addr, pm_base);
}
+
return addr;
}
}
#ifndef CONFIG_USER_ONLY
-/* The states of mstatus_fs are:
- * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
+/*
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
*/
return;
}
- if (ctx->mstatus_fs != MSTATUS_FS) {
+ if (ctx->mstatus_fs != EXT_STATUS_DIRTY) {
/* Remember the state change for the rest of the TB. */
- ctx->mstatus_fs = MSTATUS_FS;
+ ctx->mstatus_fs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- }
-
- if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
- /* Remember the stage change for the rest of the TB. */
- ctx->mstatus_hs_fs = MSTATUS_FS;
+ tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
- tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ if (ctx->virt_enabled) {
+ tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
+ tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
+ }
}
}
#else
#endif
#ifndef CONFIG_USER_ONLY
-/* The states of mstatus_vs are:
- * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
+/*
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
*/
{
TCGv tmp;
- if (ctx->mstatus_vs != MSTATUS_VS) {
+ if (ctx->mstatus_vs != EXT_STATUS_DIRTY) {
/* Remember the state change for the rest of the TB. */
- ctx->mstatus_vs = MSTATUS_VS;
+ ctx->mstatus_vs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- }
-
- if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) {
- /* Remember the stage change for the rest of the TB. */
- ctx->mstatus_hs_vs = MSTATUS_VS;
+ tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
- tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ if (ctx->virt_enabled) {
+ tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
+ tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
+ }
}
}
#else
/* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
decode_save_opc(ctx);
- gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
+ gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm));
}
static void gen_set_rm_chkfrm(DisasContext *ctx, int rm)
/* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
decode_save_opc(ctx);
- gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm));
+ gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm));
}
static int ex_plus_1(DisasContext *ctx, int nf)
} while (0)
#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
- if (!ctx->cfg_ptr->ext_##A && \
- !ctx->cfg_ptr->ext_##B) { \
+ if (!ctx->cfg_ptr->ext_##A && \
+ !ctx->cfg_ptr->ext_##B) { \
return false; \
} \
} while (0)
return 8 + reg;
}
+static int ex_sreg_register(DisasContext *ctx, int reg)
+{
+ return reg < 2 ? reg + 8 : reg + 16;
+}
+
static int ex_rvc_shiftli(DisasContext *ctx, int imm)
{
/* For RV128 a shamt of 0 means a shift by 64. */
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUState *cpu = ctx->cs;
- CPURISCVState *env = cpu->env_ptr;
+ CPURISCVState *env = cpu_env(cpu);
return cpu_ldl_code(env, pc);
}
#include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzicond.c.inc"
+#include "insn_trans/trans_rvzacas.c.inc"
#include "insn_trans/trans_rvzawrs.c.inc"
#include "insn_trans/trans_rvzicbo.c.inc"
+#include "insn_trans/trans_rvzfa.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_rvk.c.inc"
+#include "insn_trans/trans_rvvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
#include "insn_trans/trans_svinval.c.inc"
+#include "insn_trans/trans_rvbf16.c.inc"
#include "decode-xthead.c.inc"
#include "insn_trans/trans_xthead.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
+#include "insn_trans/trans_rvzce.c.inc"
+
/* Include decoders for factored-out extensions */
#include "decode-XVentanaCondOps.c.inc"
* that are tested in-order until a decoder matches onto the opcode.
*/
static const struct {
- bool (*guard_func)(DisasContext *);
+ bool (*guard_func)(const RISCVCPUConfig *);
bool (*decode_func)(DisasContext *, uint32_t);
} decoders[] = {
{ always_true_p, decode_insn32 },
};
ctx->virt_inst_excp = false;
+ ctx->cur_insn_len = insn_len(opcode);
/* Check for compressed insn */
- if (insn_len(opcode) == 2) {
+ if (ctx->cur_insn_len == 2) {
ctx->opcode = opcode;
- ctx->pc_succ_insn = ctx->base.pc_next + 2;
- if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
+ /*
+ * The Zca extension is added as way to refer to instructions in the C
+ * extension that do not include the floating-point loads and stores
+ */
+ if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) &&
+ decode_insn16(ctx, opcode)) {
return;
}
} else {
translator_lduw(env, &ctx->base,
ctx->base.pc_next + 2));
ctx->opcode = opcode32;
- ctx->pc_succ_insn = ctx->base.pc_next + 4;
for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
- if (decoders[i].guard_func(ctx) &&
+ if (decoders[i].guard_func(ctx->cfg_ptr) &&
decoders[i].decode_func(ctx, opcode32)) {
return;
}
static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cs->env_ptr;
+ CPURISCVState *env = cpu_env(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
uint32_t tb_flags = ctx->base.tb->flags;
- ctx->pc_succ_insn = ctx->base.pc_first;
+ ctx->pc_save = ctx->base.pc_first;
+ ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
- ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
- ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
+ ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
+ ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS);
ctx->priv_ver = env->priv_ver;
-#if !defined(CONFIG_USER_ONLY)
- if (riscv_has_ext(env, RVH)) {
- ctx->virt_enabled = riscv_cpu_virt_enabled(env);
- } else {
- ctx->virt_enabled = false;
- }
-#else
- ctx->virt_enabled = false;
-#endif
+ ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED);
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
ctx->cfg_ptr = &(cpu->cfg);
- ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
- ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
- ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s;
ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
- ctx->vstart = env->vstart;
+ ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->misa_mxl_max = env->misa_mxl_max;
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
+ ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs;
ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ target_ulong pc_next = ctx->base.pc_next;
+
+ if (tb_cflags(dcbase->tb) & CF_PCREL) {
+ pc_next &= ~TARGET_PAGE_MASK;
+ }
- tcg_gen_insn_start(ctx->base.pc_next, 0);
+ tcg_gen_insn_start(pc_next, 0);
ctx->insn_start = tcg_last_op();
}
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cpu->env_ptr;
+ CPURISCVState *env = cpu_env(cpu);
uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
ctx->ol = ctx->xl;
decode_opc(env, ctx, opcode16);
- ctx->base.pc_next = ctx->pc_succ_insn;
+ ctx->base.pc_next += ctx->cur_insn_len;
/* Only the first insn within a TB is allowed to cross a page boundary. */
if (ctx->base.is_jmp == DISAS_NEXT) {
switch (ctx->base.is_jmp) {
case DISAS_TOO_MANY:
- gen_goto_tb(ctx, 0, ctx->base.pc_next);
+ gen_goto_tb(ctx, 0, 0);
break;
case DISAS_NORETURN:
break;
fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
#ifndef CONFIG_USER_ONLY
- fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n",
- env->priv, env->virt);
+ fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n",
+ env->priv, env->virt_enabled);
#endif
target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
}
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
cpu_gprh[0] = NULL;
for (i = 1; i < 32; i++) {
- cpu_gpr[i] = tcg_global_mem_new(cpu_env,
+ cpu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
- cpu_gprh[i] = tcg_global_mem_new(cpu_env,
+ cpu_gprh[i] = tcg_global_mem_new(tcg_env,
offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]);
}
for (i = 0; i < 32; i++) {
- cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
}
- cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
- cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
- cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart),
+ cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc");
+ cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl");
+ cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart),
"vstart");
- load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
+ load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res),
"load_res");
- load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
+ load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
"load_val");
/* Assign PM CSRs to tcg globals */
- pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
+ pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask),
"pmmask");
- pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
+ pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase),
"pmbase");
}
projects / mirror_qemu.git / blobdiff