}
}
- if ((sew > cpu->cfg.elen)
- || vill
- || (ediv != 0)
- || (reserved != 0)) {
+ if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
/* only set vill bit. */
env->vill = 1;
env->vtype = 0;
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
{
- return (addr & env->cur_pmmask) | env->cur_pmbase;
+ return (addr & ~env->cur_pmmask) | env->cur_pmbase;
}
/*
GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq)
+static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
+ void *vd, uint32_t desc, uint32_t nf,
+ uint32_t esz, uint32_t max_elems)
+{
+ uint32_t total_elems, vlenb, registers_used;
+ uint32_t vta = vext_vta(desc);
+ int k;
+
+ if (vta == 0) {
+ return;
+ }
+
+ total_elems = vext_get_total_elems(env, desc, esz);
+ vlenb = riscv_cpu_cfg(env)->vlen >> 3;
+
+ for (k = 0; k < nf; ++k) {
+ vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz,
+ (k * max_elems + max_elems) * esz);
+ }
+
+ if (nf * max_elems % total_elems != 0) {
+ registers_used = ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
+ vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
+ registers_used * vlenb);
+ }
+}
+
/*
- *** stride: access vector element from strided memory
+ * stride: access vector element from strided memory
*/
static void
vext_ldst_stride(void *vd, void *v0, target_ulong base,
uint32_t nf = vext_nf(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
- uint32_t vta = vext_vta(desc);
uint32_t vma = vext_vma(desc);
for (i = env->vstart; i < env->vl; i++, env->vstart++) {
}
}
env->vstart = 0;
- /* set tail elements to 1s */
- for (k = 0; k < nf; ++k) {
- vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
- (k * max_elems + max_elems) * esz);
- }
- if (nf * max_elems % total_elems != 0) {
- uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
- uint32_t registers_used =
- ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
- vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
- }
+
+ vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems);
}
#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \
GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
/*
- *** unit-stride: access elements stored contiguously in memory
+ * unit-stride: access elements stored contiguously in memory
*/
-/* unmasked unit-stride load and store operation*/
+/* unmasked unit-stride load and store operation */
static void
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl,
uint32_t nf = vext_nf(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
- uint32_t vta = vext_vta(desc);
/* load bytes from guest memory */
for (i = env->vstart; i < evl; i++, env->vstart++) {
}
}
env->vstart = 0;
- /* set tail elements to 1s */
- for (k = 0; k < nf; ++k) {
- vext_set_elems_1s(vd, vta, (k * max_elems + evl) * esz,
- (k * max_elems + max_elems) * esz);
- }
- if (nf * max_elems % total_elems != 0) {
- uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
- uint32_t registers_used =
- ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
- vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
- }
+
+ vext_set_tail_elems_1s(env, evl, vd, desc, nf, esz, max_elems);
}
/*
- * masked unit-stride load and store operation will be a special case of stride,
- * stride = NF * sizeof (MTYPE)
+ * masked unit-stride load and store operation will be a special case of
+ * stride, stride = NF * sizeof (MTYPE)
*/
#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \
GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
/*
- *** unit stride mask load and store, EEW = 1
+ * unit stride mask load and store, EEW = 1
*/
void HELPER(vlm_v)(void *vd, void *v0, target_ulong base,
CPURISCVState *env, uint32_t desc)
}
/*
- *** index: access vector element from indexed memory
+ * index: access vector element from indexed memory
*/
typedef target_ulong vext_get_index_addr(target_ulong base,
uint32_t idx, void *vs2);
uint32_t vm = vext_vm(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
- uint32_t vta = vext_vta(desc);
uint32_t vma = vext_vma(desc);
/* load bytes from guest memory */
}
}
env->vstart = 0;
- /* set tail elements to 1s */
- for (k = 0; k < nf; ++k) {
- vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
- (k * max_elems + max_elems) * esz);
- }
- if (nf * max_elems % total_elems != 0) {
- uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
- uint32_t registers_used =
- ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
- vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
- }
+
+ vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems);
}
#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \
GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
/*
- *** unit-stride fault-only-fisrt load instructions
+ * unit-stride fault-only-fisrt load instructions
*/
static inline void
vext_ldff(void *vd, void *v0, target_ulong base,
uint32_t vm = vext_vm(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
- uint32_t vta = vext_vta(desc);
uint32_t vma = vext_vma(desc);
target_ulong addr, offset, remain;
- /* probe every access*/
+ /* probe every access */
for (i = env->vstart; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
}
env->vstart = 0;
- /* set tail elements to 1s */
- for (k = 0; k < nf; ++k) {
- vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
- (k * max_elems + max_elems) * esz);
- }
- if (nf * max_elems % total_elems != 0) {
- uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
- uint32_t registers_used =
- ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
- vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
- }
+
+ vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems);
}
#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \
#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
/*
- *** load and store whole register instructions
+ * load and store whole register instructions
*/
static void
vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
{
uint32_t i, k, off, pos;
uint32_t nf = vext_nf(desc);
- uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ uint32_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
uint32_t max_elems = vlenb >> log2_esz;
k = env->vstart / max_elems;
/* load/store rest of elements of current segment pointed by vstart */
for (pos = off; pos < max_elems; pos++, env->vstart++) {
target_ulong addr = base + ((pos + k * max_elems) << log2_esz);
- ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd,
+ ra);
}
k++;
}
GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
/*
- *** Vector Integer Arithmetic Instructions
+ * Vector Integer Arithmetic Instructions
*/
/* expand macro args before macro */
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
} \
- env->vstart = 0; \
+ env->vstart = 0; \
/* set tail elements to 1s */ \
vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
}
{ \
uint32_t vl = env->vl; \
uint32_t vm = vext_vm(desc); \
- uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
{ \
uint32_t vl = env->vl; \
uint32_t vm = vext_vm(desc); \
- uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f)
GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f)
-/* generate the helpers for shift instructions with one vector and one scalar */
+/*
+ * generate the helpers for shift instructions with one vector and one scalar
+ */
#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t vma = vext_vma(desc); \
uint32_t i; \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t vma = vext_vma(desc); \
uint32_t i; \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
/* Vector Integer Divide Instructions */
#define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
#define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M)
-#define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\
+#define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : \
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
-#define DO_REM(N, M) (unlikely(M == 0) ? N :\
+#define DO_REM(N, M) (unlikely(M == 0) ? N : \
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU)
GEN_VEXT_VX(vwmulsu_vx_w, 8)
/* Vector Single-Width Integer Multiply-Add Instructions */
-#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
+#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
{ \
TX1 s1 = *((T1 *)vs1 + HS1(i)); \
GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8)
/*
- *** Vector Fixed-Point Arithmetic Instructions
+ * Vector Fixed-Point Arithmetic Instructions
*/
/* Vector Single-Width Saturating Add and Subtract */
do_##NAME, ESZ); \
}
-static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
+static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a,
+ uint8_t b)
{
uint8_t res = a + b;
if (res < a) {
/* generate helpers for fixed point instructions with OPIVX format */
#define GEN_VEXT_VX_RM(NAME, ESZ) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
{ \
vext_vx_rm_2(vd, v0, s1, vs2, env, desc, \
do_##NAME, ESZ); \
return res;
}
-static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
+static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a,
+ int16_t b)
{
int16_t res = a + b;
if ((res ^ a) & (res ^ b) & INT16_MIN) {
return res;
}
-static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a,
+ int32_t b)
{
int32_t res = a + b;
if ((res ^ a) & (res ^ b) & INT32_MIN) {
return res;
}
-static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a,
+ int64_t b)
{
int64_t res = a + b;
if ((res ^ a) & (res ^ b) & INT64_MIN) {
GEN_VEXT_VX_RM(vsadd_vx_w, 4)
GEN_VEXT_VX_RM(vsadd_vx_d, 8)
-static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
+static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a,
+ uint8_t b)
{
uint8_t res = a - b;
if (res > a) {
return res;
}
-static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
+static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a,
+ int16_t b)
{
int16_t res = a - b;
if ((res ^ a) & (a ^ b) & INT16_MIN) {
return res;
}
-static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a,
+ int32_t b)
{
int32_t res = a - b;
if ((res ^ a) & (a ^ b) & INT32_MIN) {
return res;
}
-static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a,
+ int64_t b)
{
int64_t res = a - b;
if ((res ^ a) & (a ^ b) & INT64_MIN) {
return 0; /* round-down (truncate) */
}
-static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a,
+ int32_t b)
{
int64_t res = (int64_t)a + b;
uint8_t round = get_round(vxrm, res, 1);
return (res >> 1) + round;
}
-static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a,
+ int64_t b)
{
int64_t res = a + b;
uint8_t round = get_round(vxrm, res, 1);
GEN_VEXT_VX_RM(vaaddu_vx_w, 4)
GEN_VEXT_VX_RM(vaaddu_vx_d, 8)
-static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a,
+ int32_t b)
{
int64_t res = (int64_t)a - b;
uint8_t round = get_round(vxrm, res, 1);
return (res >> 1) + round;
}
-static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a,
+ int64_t b)
{
int64_t res = (int64_t)a - b;
uint8_t round = get_round(vxrm, res, 1);
res = (int16_t)a * (int16_t)b;
round = get_round(vxrm, res, 7);
- res = (res >> 7) + round;
+ res = (res >> 7) + round;
if (res > INT8_MAX) {
env->vxsat = 0x1;
res = (int32_t)a * (int32_t)b;
round = get_round(vxrm, res, 15);
- res = (res >> 15) + round;
+ res = (res >> 15) + round;
if (res > INT16_MAX) {
env->vxsat = 0x1;
res = (int64_t)a * (int64_t)b;
round = get_round(vxrm, res, 31);
- res = (res >> 31) + round;
+ res = (res >> 31) + round;
if (res > INT32_MAX) {
env->vxsat = 0x1;
uint8_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
return res;
}
static inline uint16_t
vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b)
{
uint8_t round, shift = b & 0xf;
- uint16_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
- return res;
+ return (a >> shift) + round;
}
static inline uint32_t
vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b)
{
uint8_t round, shift = b & 0x1f;
- uint32_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
- return res;
+ return (a >> shift) + round;
}
static inline uint64_t
vssrl64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b)
{
uint8_t round, shift = b & 0x3f;
- uint64_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
- return res;
+ return (a >> shift) + round;
}
RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8)
RVVCALL(OPIVV2_RM, vssrl_vv_h, OP_UUU_H, H2, H2, H2, vssrl16)
vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
{
uint8_t round, shift = b & 0x7;
- int8_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
- return res;
+ return (a >> shift) + round;
}
static inline int16_t
vssra16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
{
uint8_t round, shift = b & 0xf;
- int16_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
- return res;
+ return (a >> shift) + round;
}
static inline int32_t
vssra32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
{
uint8_t round, shift = b & 0x1f;
- int32_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
- return res;
+ return (a >> shift) + round;
}
static inline int64_t
vssra64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
{
uint8_t round, shift = b & 0x3f;
- int64_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
- return res;
+ return (a >> shift) + round;
}
RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8)
int16_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > INT8_MAX) {
env->vxsat = 0x1;
return INT8_MAX;
int32_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > INT16_MAX) {
env->vxsat = 0x1;
return INT16_MAX;
int64_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > INT32_MAX) {
env->vxsat = 0x1;
return INT32_MAX;
uint16_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > UINT8_MAX) {
env->vxsat = 0x1;
return UINT8_MAX;
uint32_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > UINT16_MAX) {
env->vxsat = 0x1;
return UINT16_MAX;
uint64_t res;
round = get_round(vxrm, a, shift);
- res = (a >> shift) + round;
+ res = (a >> shift) + round;
if (res > UINT32_MAX) {
env->vxsat = 0x1;
return UINT32_MAX;
GEN_VEXT_VX_RM(vnclipu_wx_w, 4)
/*
- *** Vector Float Point Arithmetic Instructions
+ * Vector Float Point Arithmetic Instructions
*/
/* Vector Single-Width Floating-Point Add/Subtract Instructions */
#define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t total_elems = \
- vext_get_total_elems(env, desc, ESZ); \
+ vext_get_total_elems(env, desc, ESZ); \
uint32_t vta = vext_vta(desc); \
uint32_t vma = vext_vma(desc); \
uint32_t i; \
static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s)
{
return float32_add(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), s);
+ float16_to_float32(b, true, s), s);
}
static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s)
{
return float64_add(float32_to_float64(a, s),
- float32_to_float64(b, s), s);
+ float32_to_float64(b, s), s);
}
static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s)
{
return float32_sub(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), s);
+ float16_to_float32(b, true, s), s);
}
static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s)
{
return float64_sub(float32_to_float64(a, s),
- float32_to_float64(b, s), s);
+ float32_to_float64(b, s), s);
}
static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
{
return float32_mul(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), s);
+ float16_to_float32(b, true, s), s);
}
static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
{
return float64_mul(float32_to_float64(a, s),
- float32_to_float64(b, s), s);
+ float32_to_float64(b, s), s);
}
RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
#define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
- CPURISCVState *env) \
+ CPURISCVState *env) \
{ \
TX1 s1 = *((T1 *)vs1 + HS1(i)); \
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
#define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
- CPURISCVState *env) \
+ CPURISCVState *env) \
{ \
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
TD d = *((TD *)vd + HD(i)); \
static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
- return float16_muladd(a, b, d,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float16_muladd(a, b, d, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
static uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
- return float32_muladd(a, b, d,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float32_muladd(a, b, d, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
- return float64_muladd(a, b, d,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float64_muladd(a, b, d, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
- return float16_muladd(d, b, a,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float16_muladd(d, b, a, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
static uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s)
{
- return float32_muladd(d, b, a,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float32_muladd(d, b, a, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
{
- return float64_muladd(d, b, a,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float64_muladd(d, b, a, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), d, 0, s);
+ float16_to_float32(b, true, s), d, 0, s);
}
static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
return float64_muladd(float32_to_float64(a, s),
- float32_to_float64(b, s), d, 0, s);
+ float32_to_float64(b, s), d, 0, s);
}
RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16)
static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), d,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ float16_to_float32(b, true, s), d,
+ float_muladd_negate_c | float_muladd_negate_product,
+ s);
}
static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
- return float64_muladd(float32_to_float64(a, s),
- float32_to_float64(b, s), d,
- float_muladd_negate_c | float_muladd_negate_product, s);
+ return float64_muladd(float32_to_float64(a, s), float32_to_float64(b, s),
+ d, float_muladd_negate_c |
+ float_muladd_negate_product, s);
}
RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), d,
- float_muladd_negate_c, s);
+ float16_to_float32(b, true, s), d,
+ float_muladd_negate_c, s);
}
static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
return float64_muladd(float32_to_float64(a, s),
- float32_to_float64(b, s), d,
- float_muladd_negate_c, s);
+ float32_to_float64(b, s), d,
+ float_muladd_negate_c, s);
}
RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16)
static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
- float16_to_float32(b, true, s), d,
- float_muladd_negate_product, s);
+ float16_to_float32(b, true, s), d,
+ float_muladd_negate_product, s);
}
static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
{
return float64_muladd(float32_to_float64(a, s),
- float32_to_float64(b, s), d,
- float_muladd_negate_product, s);
+ float32_to_float64(b, s), d,
+ float_muladd_negate_product, s);
}
RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16)
#define OP_UU_W uint32_t, uint32_t, uint32_t
#define OP_UU_D uint64_t, uint64_t, uint64_t
-#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
+#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, void *vs2, int i, \
- CPURISCVState *env) \
+ CPURISCVState *env) \
{ \
TX2 s2 = *((T2 *)vs2 + HS2(i)); \
*((TD *)vd + HD(i)) = OP(s2, &env->fp_status); \
#define GEN_VEXT_V_ENV(NAME, ESZ) \
void HELPER(NAME)(void *vd, void *v0, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
+ CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
}
int idx = ((exp & 1) << (precision - 1)) |
- (frac >> (frac_size - precision + 1));
+ (frac >> (frac_size - precision + 1));
uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
- (frac_size - precision);
+ (frac_size - precision);
uint64_t out_exp = (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2;
uint64_t val = 0;
* frsqrt7(-subnormal) = canonical NaN
*/
if (float16_is_signaling_nan(f, s) ||
- (float16_is_infinity(f) && sign) ||
- (float16_is_normal(f) && sign) ||
- (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) {
+ (float16_is_infinity(f) && sign) ||
+ (float16_is_normal(f) && sign) ||
+ (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) {
s->float_exception_flags |= float_flag_invalid;
return float16_default_nan(s);
}
* frsqrt7(-subnormal) = canonical NaN
*/
if (float32_is_signaling_nan(f, s) ||
- (float32_is_infinity(f) && sign) ||
- (float32_is_normal(f) && sign) ||
- (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) {
+ (float32_is_infinity(f) && sign) ||
+ (float32_is_normal(f) && sign) ||
+ (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) {
s->float_exception_flags |= float_flag_invalid;
return float32_default_nan(s);
}
* frsqrt7(-subnormal) = canonical NaN
*/
if (float64_is_signaling_nan(f, s) ||
- (float64_is_infinity(f) && sign) ||
- (float64_is_normal(f) && sign) ||
- (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) {
+ (float64_is_infinity(f) && sign) ||
+ (float64_is_normal(f) && sign) ||
+ (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) {
s->float_exception_flags |= float_flag_invalid;
return float64_default_nan(s);
}
((s->float_rounding_mode == float_round_up) && sign)) {
/* Return greatest/negative finite value. */
return (sign << (exp_size + frac_size)) |
- (MAKE_64BIT_MASK(frac_size, exp_size) - 1);
+ (MAKE_64BIT_MASK(frac_size, exp_size) - 1);
} else {
/* Return +-inf. */
return (sign << (exp_size + frac_size)) |
- MAKE_64BIT_MASK(frac_size, exp_size);
+ MAKE_64BIT_MASK(frac_size, exp_size);
}
}
}
int idx = frac >> (frac_size - precision);
uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
- (frac_size - precision);
+ (frac_size - precision);
uint64_t out_exp = 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp;
if (out_exp == 0 || out_exp == UINT64_MAX) {
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t vma = vext_vma(desc); \
uint32_t i; \
DO_OP(s2, s1, &env->fp_status)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t vma = vext_vma(desc); \
uint32_t i; \
DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail-agnostic */ \
- /* set tail elements to 1s */ \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- *((ETYPE *)vd + H(i)) \
- = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
+ *((ETYPE *)vd + H(i)) = \
+ (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
} \
env->vstart = 0; \
/* set tail elements to 1s */ \
#define WOP_UU_B uint16_t, uint8_t, uint8_t
#define WOP_UU_H uint32_t, uint16_t, uint16_t
#define WOP_UU_W uint64_t, uint32_t, uint32_t
-/* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
+/*
+ * vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.
+ */
RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32)
RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64)
GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 4)
GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 4)
GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 8)
-/* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
+/*
+ * vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float.
+ */
RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 8)
/*
- * vfwcvt.f.f.v vd, vs2, vm
- * Convert single-width float to double-width float.
+ * vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float.
*/
static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
{
GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2)
GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4)
-/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
+/*
+ * vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float.
+ */
RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2)
GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
/*
- *** Vector Reduction Operations
+ * Vector Reduction Operations
*/
/* Vector Single-Width Integer Reduction Instructions */
#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
/* Maximum value */
-GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_number)
-GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maximum_number)
-GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maximum_number)
+GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2,
+ float16_maximum_number)
+GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4,
+ float32_maximum_number)
+GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8,
+ float64_maximum_number)
/* Minimum value */
-GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minimum_number)
-GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minimum_number)
-GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minimum_number)
+GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2,
+ float16_minimum_number)
+GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4,
+ float32_minimum_number)
+GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8,
+ float64_minimum_number)
/* Vector Widening Floating-Point Add Instructions */
static uint32_t fwadd16(uint32_t a, uint16_t b, float_status *s)
GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32)
/*
- *** Vector Mask Operations
+ * Vector Mask Operations
*/
/* Vector Mask-Register Logical Instructions */
#define GEN_VEXT_MASK_VV(NAME, OP) \
uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
int a, b; \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
env->vstart = 0; \
- /* mask destination register are always tail- \
- * agnostic \
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
*/ \
- /* set tail elements to 1s */ \
if (vta_all_1s) { \
for (; i < total_elems; i++) { \
vext_set_elem_mask(vd, i, 1); \
return cnt;
}
-/* vfirst find-first-set mask bit*/
+/* vfirst find-first-set mask bit */
target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
{
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
- uint32_t total_elems = env_archcpu(env)->cfg.vlen;
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlen;
uint32_t vta_all_1s = vext_vta_all_1s(desc);
uint32_t vma = vext_vma(desc);
int i;
}
}
env->vstart = 0;
- /* mask destination register are always tail-agnostic */
- /* set tail elements to 1s */
+ /*
+ * mask destination register are always tail-agnostic
+ * set tail elements to 1s
+ */
if (vta_all_1s) {
for (; i < total_elems; i++) {
vext_set_elem_mask(vd, i, 1);
GEN_VEXT_VID_V(vid_v_d, uint64_t, H8)
/*
- *** Vector Permutation Instructions
+ * Vector Permutation Instructions
*/
/* Vector Slide Instructions */
GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
#define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \
-static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
+static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
{ \
typedef uint##BITWIDTH##_t ETYPE; \
uint32_t vm = vext_vm(desc); \
GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
#define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \
-static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
+static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
{ \
typedef uint##BITWIDTH##_t ETYPE; \
uint32_t vm = vext_vm(desc); \
projects / mirror_qemu.git / blobdiff