# define gen_helper_restored(E) qemu_build_not_reached()
# define gen_helper_retry(E) qemu_build_not_reached()
# define gen_helper_saved(E) qemu_build_not_reached()
-# define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached()
# define gen_helper_set_softint(E, S) qemu_build_not_reached()
# define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached()
# define gen_helper_tick_set_count(P, S) qemu_build_not_reached()
# define gen_helper_tick_set_limit(P, S) qemu_build_not_reached()
-# define gen_helper_udivx(D, E, A, B) qemu_build_not_reached()
# define gen_helper_wrccr(E, S) qemu_build_not_reached()
# define gen_helper_wrcwp(E, S) qemu_build_not_reached()
# define gen_helper_wrgl(E, S) qemu_build_not_reached()
target_ulong jump_pc[2];
int mem_idx;
+ bool cpu_cond_live;
bool fpu_enabled;
bool address_mask_32bit;
#ifndef CONFIG_USER_ONLY
gen_op_multiply(dst, src1, src2, 1);
}
-static void gen_op_udivx(TCGv dst, TCGv src1, TCGv src2)
-{
- gen_helper_udivx(dst, tcg_env, src1, src2);
-}
-
-static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
-{
- gen_helper_sdivx(dst, tcg_env, src1, src2);
-}
-
-static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2)
-{
-#ifdef TARGET_SPARC64
- gen_helper_udiv(dst, tcg_env, src1, src2);
- tcg_gen_ext32u_tl(dst, dst);
-#else
- TCGv_i64 t64 = tcg_temp_new_i64();
- gen_helper_udiv(t64, tcg_env, src1, src2);
- tcg_gen_trunc_i64_tl(dst, t64);
-#endif
-}
-
static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
{
#ifdef TARGET_SPARC64
tcg_gen_xori_tl(dst, dst, 0x1);
}
+static void finishing_insn(DisasContext *dc)
+{
+ /*
+ * From here, there is no future path through an unwinding exception.
+ * If the current insn cannot raise an exception, the computation of
+ * cpu_cond may be able to be elided.
+ */
+ if (dc->cpu_cond_live) {
+ tcg_gen_discard_tl(cpu_cond);
+ dc->cpu_cond_live = false;
+ }
+}
+
static void gen_generic_branch(DisasContext *dc)
{
TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]);
static void gen_exception(DisasContext *dc, int which)
{
+ finishing_insn(dc);
save_state(dc);
gen_helper_raise_exception(tcg_env, tcg_constant_i32(which));
dc->base.is_jmp = DISAS_NORETURN;
static void gen_mov_pc_npc(DisasContext *dc)
{
+ finishing_insn(dc);
+
if (dc->npc & 3) {
switch (dc->npc) {
case JUMP_PC:
}
}
-// Inverted logic
-static const TCGCond gen_tcg_cond_reg[8] = {
- TCG_COND_NEVER, /* reserved */
- TCG_COND_NE,
- TCG_COND_GT,
- TCG_COND_GE,
- TCG_COND_NEVER, /* reserved */
- TCG_COND_EQ,
- TCG_COND_LE,
- TCG_COND_LT,
-};
-
-static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
+static bool gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
{
- cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
+ static const TCGCond cond_reg[4] = {
+ TCG_COND_NEVER, /* reserved */
+ TCG_COND_EQ,
+ TCG_COND_LE,
+ TCG_COND_LT,
+ };
+ TCGCond tcond;
+
+ if ((cond & 3) == 0) {
+ return false;
+ }
+ tcond = cond_reg[cond & 3];
+ if (cond & 4) {
+ tcond = tcg_invert_cond(tcond);
+ }
+
+ cmp->cond = tcond;
cmp->c1 = tcg_temp_new();
cmp->c2 = 0;
tcg_gen_mov_tl(cmp->c1, r_src);
+ return true;
}
static void gen_op_clear_ieee_excp_and_FTT(void)
{
TCGLabel *l1;
+ finishing_insn(dc);
+
if (dc->npc & 3) {
switch (dc->npc) {
case DYNAMIC_PC:
target_ulong dest = address_mask_i(dc, dc->pc + disp * 4);
target_ulong npc;
+ finishing_insn(dc);
+
if (cmp->cond == TCG_COND_ALWAYS) {
if (annul) {
dc->pc = dest;
} else {
tcg_gen_setcondi_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2);
}
+ dc->cpu_cond_live = true;
}
}
return true;
if (!avail_64(dc)) {
return false;
}
- if (gen_tcg_cond_reg[a->cond] == TCG_COND_NEVER) {
+ if (!gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1))) {
return false;
}
-
- gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
return advance_jump_cond(dc, &cmp, a->a, a->i);
}
tcg_gen_addi_i32(trap, trap, TT_TRAP);
}
+ finishing_insn(dc);
+
/* Trap always. */
if (cond == 8) {
save_state(dc);
static void do_wrpowerdown(DisasContext *dc, TCGv src)
{
+ finishing_insn(dc);
save_state(dc);
gen_helper_power_down(tcg_env);
}
TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL)
TRANS(MULScc, ALL, do_arith, a, NULL, NULL, gen_op_mulscc)
-TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL, NULL)
-TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL, NULL)
-TRANS(UDIV, DIV, do_arith, a, gen_op_udiv, NULL, gen_op_udivcc)
+TRANS(UDIVcc, DIV, do_arith, a, NULL, NULL, gen_op_udivcc)
TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL, gen_op_sdivcc)
/* TODO: Should have feature bit -- comes in with UltraSparc T2. */
return do_logic(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl);
}
+static bool trans_UDIV(DisasContext *dc, arg_r_r_ri *a)
+{
+ TCGv_i64 t1, t2;
+ TCGv dst;
+
+ if (!avail_DIV(dc)) {
+ return false;
+ }
+ /* For simplicity, we under-decoded the rs2 form. */
+ if (!a->imm && a->rs2_or_imm & ~0x1f) {
+ return false;
+ }
+
+ if (unlikely(a->rs2_or_imm == 0)) {
+ gen_exception(dc, TT_DIV_ZERO);
+ return true;
+ }
+
+ if (a->imm) {
+ t2 = tcg_constant_i64((uint32_t)a->rs2_or_imm);
+ } else {
+ TCGLabel *lab;
+ TCGv_i32 n2;
+
+ finishing_insn(dc);
+ flush_cond(dc);
+
+ n2 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(n2, cpu_regs[a->rs2_or_imm]);
+
+ lab = delay_exception(dc, TT_DIV_ZERO);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, n2, 0, lab);
+
+ t2 = tcg_temp_new_i64();
+#ifdef TARGET_SPARC64
+ tcg_gen_ext32u_i64(t2, cpu_regs[a->rs2_or_imm]);
+#else
+ tcg_gen_extu_i32_i64(t2, cpu_regs[a->rs2_or_imm]);
+#endif
+ }
+
+ t1 = tcg_temp_new_i64();
+ tcg_gen_concat_tl_i64(t1, gen_load_gpr(dc, a->rs1), cpu_y);
+
+ tcg_gen_divu_i64(t1, t1, t2);
+ tcg_gen_umin_i64(t1, t1, tcg_constant_i64(UINT32_MAX));
+
+ dst = gen_dest_gpr(dc, a->rd);
+ tcg_gen_trunc_i64_tl(dst, t1);
+ gen_store_gpr(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
+static bool trans_UDIVX(DisasContext *dc, arg_r_r_ri *a)
+{
+ TCGv dst, src1, src2;
+
+ if (!avail_64(dc)) {
+ return false;
+ }
+ /* For simplicity, we under-decoded the rs2 form. */
+ if (!a->imm && a->rs2_or_imm & ~0x1f) {
+ return false;
+ }
+
+ if (unlikely(a->rs2_or_imm == 0)) {
+ gen_exception(dc, TT_DIV_ZERO);
+ return true;
+ }
+
+ if (a->imm) {
+ src2 = tcg_constant_tl(a->rs2_or_imm);
+ } else {
+ TCGLabel *lab;
+
+ finishing_insn(dc);
+ flush_cond(dc);
+
+ lab = delay_exception(dc, TT_DIV_ZERO);
+ src2 = cpu_regs[a->rs2_or_imm];
+ tcg_gen_brcondi_tl(TCG_COND_EQ, src2, 0, lab);
+ }
+
+ dst = gen_dest_gpr(dc, a->rd);
+ src1 = gen_load_gpr(dc, a->rs1);
+
+ tcg_gen_divu_tl(dst, src1, src2);
+ gen_store_gpr(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
+static bool trans_SDIVX(DisasContext *dc, arg_r_r_ri *a)
+{
+ TCGv dst, src1, src2;
+
+ if (!avail_64(dc)) {
+ return false;
+ }
+ /* For simplicity, we under-decoded the rs2 form. */
+ if (!a->imm && a->rs2_or_imm & ~0x1f) {
+ return false;
+ }
+
+ if (unlikely(a->rs2_or_imm == 0)) {
+ gen_exception(dc, TT_DIV_ZERO);
+ return true;
+ }
+
+ dst = gen_dest_gpr(dc, a->rd);
+ src1 = gen_load_gpr(dc, a->rs1);
+
+ if (a->imm) {
+ if (unlikely(a->rs2_or_imm == -1)) {
+ tcg_gen_neg_tl(dst, src1);
+ gen_store_gpr(dc, a->rd, dst);
+ return advance_pc(dc);
+ }
+ src2 = tcg_constant_tl(a->rs2_or_imm);
+ } else {
+ TCGLabel *lab;
+ TCGv t1, t2;
+
+ finishing_insn(dc);
+ flush_cond(dc);
+
+ lab = delay_exception(dc, TT_DIV_ZERO);
+ src2 = cpu_regs[a->rs2_or_imm];
+ tcg_gen_brcondi_tl(TCG_COND_EQ, src2, 0, lab);
+
+ /*
+ * Need to avoid INT64_MIN / -1, which will trap on x86 host.
+ * Set SRC2 to 1 as a new divisor, to produce the correct result.
+ */
+ t1 = tcg_temp_new();
+ t2 = tcg_temp_new();
+ tcg_gen_setcondi_tl(TCG_COND_EQ, t1, src1, (target_long)INT64_MIN);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, t2, src2, -1);
+ tcg_gen_and_tl(t1, t1, t2);
+ tcg_gen_movcond_tl(TCG_COND_NE, t1, t1, tcg_constant_tl(0),
+ tcg_constant_tl(1), src2);
+ src2 = t1;
+ }
+
+ tcg_gen_div_tl(dst, src1, src2);
+ gen_store_gpr(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
static bool gen_edge(DisasContext *dc, arg_r_r_r *a,
int width, bool cc, bool left)
{
if (src2 == NULL) {
return false;
}
- gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
+ if (!gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1))) {
+ return false;
+ }
return do_mov_cond(dc, &cmp, a->rd, src2);
}
static bool do_return(DisasContext *dc, int rd, TCGv src)
{
gen_check_align(dc, src, 3);
+ gen_helper_restore(tcg_env);
gen_mov_pc_npc(dc);
tcg_gen_mov_tl(cpu_npc, src);
gen_address_mask(dc, cpu_npc);
- gen_helper_restore(tcg_env);
dc->npc = DYNAMIC_PC_LOOKUP;
return true;
}
{
DisasCompare cmp;
+ if (!gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1))) {
+ return false;
+ }
if (gen_trap_ifnofpu(dc)) {
return true;
}
}
gen_op_clear_ieee_excp_and_FTT();
- gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
func(dc, &cmp, a->rd, a->rs2);
return advance_pc(dc);
}
DisasDelayException *e, *e_next;
bool may_lookup;
+ finishing_insn(dc);
+
switch (dc->base.is_jmp) {
case DISAS_NEXT:
case DISAS_TOO_MANY:
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc = {};
projects / mirror_qemu.git / blobdiff