#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
-#include "qemu-common.h"
+#include "fpu/softfloat.h"
+#include "qemu/module.h"
#include "migration/vmstate.h"
#endif
}
-/* CPUClass::reset() */
-static void xtensa_cpu_reset(CPUState *s)
+#ifdef CONFIG_USER_ONLY
+static bool abi_call0;
+
+void xtensa_set_abi_call0(void)
+{
+ abi_call0 = true;
+}
+
+bool xtensa_abi_call0(void)
{
+ return abi_call0;
+}
+#endif
+
+static void xtensa_cpu_reset(DeviceState *dev)
+{
+ CPUState *s = CPU(dev);
XtensaCPU *cpu = XTENSA_CPU(s);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
CPUXtensaState *env = &cpu->env;
+ bool dfpu = xtensa_option_enabled(env->config,
+ XTENSA_OPTION_DFP_COPROCESSOR);
- xcc->parent_reset(s);
+ xcc->parent_reset(dev);
- env->exception_taken = 0;
env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
env->sregs[LITBASE] &= ~1;
#ifndef CONFIG_USER_ONLY
XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
env->pending_irq_level = 0;
#else
- env->sregs[PS] =
- (xtensa_option_enabled(env->config,
- XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) |
- PS_UM | (3 << PS_RING_SHIFT);
+ env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
+ if (xtensa_option_enabled(env->config,
+ XTENSA_OPTION_WINDOWED_REGISTER) &&
+ !xtensa_abi_call0()) {
+ env->sregs[PS] |= PS_WOE;
+ }
+ env->sregs[CPENABLE] = 0xff;
#endif
env->sregs[VECBASE] = env->config->vecbase;
env->sregs[IBREAKENABLE] = 0;
env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
- env->sregs[CACHEATTR] = 0x22222222;
env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
env->sregs[CONFIGID0] = env->config->configid[0];
env->sregs[CONFIGID1] = env->config->configid[1];
+ env->exclusive_addr = -1;
#ifndef CONFIG_USER_ONLY
reset_mmu(env);
s->halted = env->runstall;
#endif
+ set_no_signaling_nans(!dfpu, &env->fp_status);
+ set_use_first_nan(!dfpu, &env->fp_status);
}
static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
static void xtensa_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
XtensaCPU *cpu = XTENSA_CPU(obj);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
CPUXtensaState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
env->config = xcc->config;
#ifndef CONFIG_USER_ONLY
#endif
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps xtensa_sysemu_ops = {
+};
+#endif
+
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps xtensa_tcg_ops = {
+ .initialize = xtensa_translate_init,
+ .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
+ .tlb_fill = xtensa_cpu_tlb_fill,
+ .debug_excp_handler = xtensa_breakpoint_handler,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = xtensa_cpu_do_interrupt,
+ .do_transaction_failed = xtensa_cpu_do_transaction_failed,
+ .do_unaligned_access = xtensa_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
&xcc->parent_realize);
- xcc->parent_reset = cc->reset;
- cc->reset = xtensa_cpu_reset;
+ device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;
- cc->do_interrupt = xtensa_cpu_do_interrupt;
- cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
- cc->tlb_fill = xtensa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
+ cc->sysemu_ops = &xtensa_sysemu_ops;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
- cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
+ dc->vmsd = &vmstate_xtensa_cpu;
#endif
- cc->debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
- cc->tcg_initialize = xtensa_translate_init;
- dc->vmsd = &vmstate_xtensa_cpu;
+ cc->tcg_ops = &xtensa_tcg_ops;
}
static const TypeInfo xtensa_cpu_type_info = {