};
int i;
- cpu_pc = tcg_global_mem_new_i32(cpu_env,
+ cpu_pc = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, pc), "pc");
for (i = 0; i < 16; i++) {
- cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_R[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, regs[i]),
regnames[i]);
}
for (i = 0; i < 16; i++) {
- cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_FR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
fregs[i].f32[FP_F32_LOW]),
fregnames[i]);
}
for (i = 0; i < 16; i++) {
- cpu_FRD[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_FRD[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUXtensaState,
fregs[i].f64),
fregnames[i]);
}
for (i = 0; i < 4; i++) {
- cpu_MR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_MR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[MR + i]),
mregnames[i]);
}
for (i = 0; i < 16; i++) {
- cpu_BR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_BR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
if (i % 4 == 0) {
- cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env,
+ cpu_BR4[i / 4] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
}
if (i % 8 == 0) {
- cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env,
+ cpu_BR8[i / 8] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
for (i = 0; i < 256; ++i) {
if (sr_name[i]) {
- cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_SR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[i]),
sr_name[i]);
for (i = 0; i < 256; ++i) {
if (ur_name[i]) {
- cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_UR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
uregs[i]),
ur_name[i]);
}
cpu_windowbase_next =
- tcg_global_mem_new_i32(cpu_env,
+ tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, windowbase_next),
"windowbase_next");
cpu_exclusive_addr =
- tcg_global_mem_new_i32(cpu_env,
+ tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, exclusive_addr),
"exclusive_addr");
cpu_exclusive_val =
- tcg_global_mem_new_i32(cpu_env,
+ tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, exclusive_val),
"exclusive_val");
}
static void gen_exception(DisasContext *dc, int excp)
{
- gen_helper_exception(cpu_env, tcg_constant_i32(excp));
+ gen_helper_exception(tcg_env, tcg_constant_i32(excp));
}
static void gen_exception_cause(DisasContext *dc, uint32_t cause)
{
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_exception_cause(cpu_env, pc, tcg_constant_i32(cause));
+ gen_helper_exception_cause(tcg_env, pc, tcg_constant_i32(cause));
if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) {
dc->base.is_jmp = DISAS_NORETURN;
static void gen_debug_exception(DisasContext *dc, uint32_t cause)
{
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_debug_exception(cpu_env, pc, tcg_constant_i32(cause));
+ gen_helper_debug_exception(tcg_env, pc, tcg_constant_i32(cause));
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
dc->base.is_jmp = DISAS_NORETURN;
}
TCGv_i32 pc = tcg_constant_i32(dc->pc);
TCGv_i32 w = tcg_constant_i32(r / 4);
- gen_helper_window_check(cpu_env, pc, w);
+ gen_helper_window_check(tcg_env, pc, w);
dc->base.is_jmp = DISAS_NORETURN;
return false;
}
#ifndef CONFIG_USER_ONLY
if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
translator_io_start(&dc->base);
- gen_helper_check_interrupts(cpu_env);
+ gen_helper_check_interrupts(tcg_env);
}
#endif
if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
- gen_helper_sync_windowbase(cpu_env);
+ gen_helper_sync_windowbase(tcg_env);
}
if (op_flags & XTENSA_OP_EXIT_TB_M1) {
slot = -1;
if (op_flags & XTENSA_OP_UNDERFLOW) {
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_test_underflow_retw(cpu_env, pc);
+ gen_helper_test_underflow_retw(tcg_env, pc);
}
if (op_flags & XTENSA_OP_ALLOCA) {
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_movsp(cpu_env, pc);
+ gen_helper_movsp(tcg_env, pc);
}
if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
return xtensa_op0_insn_len(dc, b0);
}
-static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
-{
- unsigned i;
-
- for (i = 0; i < dc->config->nibreak; ++i) {
- if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
- env->sregs[IBREAKA + i] == dc->pc) {
- gen_debug_exception(dc, DEBUGCAUSE_IB);
- break;
- }
- }
-}
-
static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUXtensaState *env = cpu->env_ptr;
+ CPUXtensaState *env = cpu_env(cpu);
uint32_t tb_flags = dc->base.tb->flags;
dc->config = env->config;
static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUXtensaState *env = cpu->env_ptr;
+ CPUXtensaState *env = cpu_env(cpu);
target_ulong page_start;
/* These two conditions only apply to the first insn in the TB,
gen_set_label(label);
}
- if (dc->debug) {
- gen_ibreak_check(env, dc);
- }
-
disas_xtensa_insn(env, dc);
if (dc->icount) {
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc = {};
translator_loop(cpu, tb, max_insns, pc, host_pc,
TCGv_i32 pc = tcg_constant_i32(dc->pc);
TCGv_i32 s = tcg_constant_i32(arg[0].imm);
TCGv_i32 imm = tcg_constant_i32(arg[1].imm);
- gen_helper_entry(cpu_env, pc, s, imm);
+ gen_helper_entry(tcg_env, pc, s, imm);
}
static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_movi_i32(cpu_pc, dc->pc);
tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
- gen_helper_itlb_hit_test(cpu_env, addr);
+ gen_helper_itlb_hit_test(tcg_env, addr);
#endif
}
#ifndef CONFIG_USER_ONLY
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
- gen_helper_itlb(cpu_env, arg[0].in, dtlb);
+ gen_helper_itlb(tcg_env, arg[0].in, dtlb);
#endif
}
if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_check_exclusive(cpu_env, pc, addr,
+ gen_helper_check_exclusive(tcg_env, pc, addr,
tcg_constant_i32(is_write));
}
}
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
tcg_gen_movi_i32(cpu_pc, dc->pc);
- gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
+ gen_helper_ptlb(arg[0].out, tcg_env, arg[1].in, dtlb);
#endif
}
{
#ifndef CONFIG_USER_ONLY
tcg_gen_movi_i32(cpu_pc, dc->pc);
- gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_pptlb(arg[0].out, tcg_env, arg[1].in);
#endif
}
static void translate_rer(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_rer(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_rer(arg[0].out, tcg_env, arg[1].in);
}
static void translate_ret(DisasContext *dc, const OpcodeArg arg[],
} else {
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_test_ill_retw(cpu_env, pc);
+ gen_helper_test_ill_retw(tcg_env, pc);
return 0;
}
}
cpu_SR[WINDOW_START], tmp);
tcg_gen_movi_i32(tmp, dc->pc);
tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30);
- gen_helper_retw(cpu_env, cpu_R[0]);
+ gen_helper_retw(tcg_env, cpu_R[0]);
gen_jump(dc, tmp);
}
cpu_SR[WINDOW_START], tmp);
}
- gen_helper_restore_owb(cpu_env);
+ gen_helper_restore_owb(tcg_env);
gen_jump(dc, cpu_SR[EPC1]);
}
{
#ifndef CONFIG_USER_ONLY
translator_io_start(&dc->base);
- gen_helper_update_ccount(cpu_env);
+ gen_helper_update_ccount(tcg_env);
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
#endif
}
};
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
- helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
+ helper[par[1]](arg[0].out, tcg_env, arg[1].in, dtlb);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_rptlb0(arg[0].out, tcg_env, arg[1].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_rptlb1(arg[0].out, tcg_env, arg[1].in);
#endif
}
{
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_check_atomctl(cpu_env, pc, addr);
+ gen_helper_check_atomctl(tcg_env, pc, addr);
}
#endif
static void translate_sext(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- int shift = 31 - arg[2].imm;
-
- if (shift == 24) {
- tcg_gen_ext8s_i32(arg[0].out, arg[1].in);
- } else if (shift == 16) {
- tcg_gen_ext16s_i32(arg[0].out, arg[1].in);
- } else {
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_shli_i32(tmp, arg[1].in, shift);
- tcg_gen_sari_i32(arg[0].out, tmp, shift);
- }
+ tcg_gen_sextract_i32(arg[0].out, arg[1].in, 0, arg[2].imm + 1);
}
static uint32_t test_exceptions_simcall(DisasContext *dc,
{
#ifndef CONFIG_USER_ONLY
if (semihosting_enabled(dc->cring != 0)) {
- gen_helper_simcall(cpu_env);
+ gen_helper_simcall(tcg_env);
}
#endif
}
TCGv_i32 pc = tcg_constant_i32(dc->base.pc_next);
translator_io_start(&dc->base);
- gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm));
+ gen_helper_waiti(tcg_env, pc, tcg_constant_i32(arg[0].imm));
#endif
}
#ifndef CONFIG_USER_ONLY
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
- gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
+ gen_helper_wtlb(tcg_env, arg[0].in, arg[1].in, dtlb);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in);
+ gen_helper_wptlb(tcg_env, arg[0].in, arg[1].in);
#endif
}
static void translate_wer(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wer(cpu_env, arg[0].in, arg[1].in);
+ gen_helper_wer(tcg_env, arg[0].in, arg[1].in);
}
static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
assert(id < dc->config->nccompare);
translator_io_start(&dc->base);
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
- gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id));
+ gen_helper_update_ccompare(tcg_env, tcg_constant_i32(id));
#endif
}
{
#ifndef CONFIG_USER_ONLY
translator_io_start(&dc->base);
- gen_helper_wsr_ccount(cpu_env, arg[0].in);
+ gen_helper_wsr_ccount(tcg_env, arg[0].in);
#endif
}
unsigned id = par[0] - DBREAKA;
assert(id < dc->config->ndbreak);
- gen_helper_wsr_dbreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
+ gen_helper_wsr_dbreaka(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif
}
unsigned id = par[0] - DBREAKC;
assert(id < dc->config->ndbreak);
- gen_helper_wsr_dbreakc(cpu_env, tcg_constant_i32(id), arg[0].in);
+ gen_helper_wsr_dbreakc(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif
}
unsigned id = par[0] - IBREAKA;
assert(id < dc->config->nibreak);
- gen_helper_wsr_ibreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
+ gen_helper_wsr_ibreaka(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_ibreakenable(cpu_env, arg[0].in);
+ gen_helper_wsr_ibreakenable(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_intclear(cpu_env, arg[0].in);
+ gen_helper_intclear(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_intset(cpu_env, arg[0].in);
+ gen_helper_intset(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_memctl(cpu_env, arg[0].in);
+ gen_helper_wsr_memctl(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_mpuenb(cpu_env, arg[0].in);
+ gen_helper_wsr_mpuenb(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_rasid(cpu_env, arg[0].in);
+ gen_helper_wsr_rasid(tcg_env, arg[0].in);
#endif
}
TCGv_i32 tmp = tcg_temp_new_i32();
translator_io_start(&dc->base);
- gen_helper_update_ccount(cpu_env);
+ gen_helper_update_ccount(tcg_env);
tcg_gen_mov_i32(tmp, cpu_SR[par[0]]);
- gen_helper_wsr_ccount(cpu_env, arg[0].in);
+ gen_helper_wsr_ccount(tcg_env, arg[0].in);
tcg_gen_mov_i32(arg[0].out, tmp);
#endif
static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_add_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
}
tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm);
tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
- helper[par[0]](res, cpu_env, arg[1].in, arg[2].in);
+ helper[par[0]](res, tcg_env, arg[1].in, arg[2].in);
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
get_f32_i2(arg, arg32, 1, 2);
- helper[par[0]](res, cpu_env, arg32[1].in, arg32[2].in);
+ helper[par[0]](res, tcg_env, arg32[1].in, arg32[2].in);
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
if (par[0]) {
- gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_uitof_d(arg[0].out, tcg_env, arg[1].in, scale);
} else {
- gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_itof_d(arg[0].out, tcg_env, arg[1].in, scale);
}
}
get_f32_o1(arg, arg32, 0);
if (par[0]) {
- gen_helper_uitof_s(arg32[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_uitof_s(arg32[0].out, tcg_env, arg[1].in, scale);
} else {
- gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_itof_s(arg32[0].out, tcg_env, arg[1].in, scale);
}
put_f32_o1(arg, arg32, 0);
}
TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
if (par[1]) {
- gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in,
+ gen_helper_ftoui_d(arg[0].out, tcg_env, arg[1].in,
rounding_mode, scale);
} else {
- gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in,
+ gen_helper_ftoi_d(arg[0].out, tcg_env, arg[1].in,
rounding_mode, scale);
}
}
get_f32_i1(arg, arg32, 1);
if (par[1]) {
- gen_helper_ftoui_s(arg[0].out, cpu_env, arg32[1].in,
+ gen_helper_ftoui_s(arg[0].out, tcg_env, arg32[1].in,
rounding_mode, scale);
} else {
- gen_helper_ftoi_s(arg[0].out, cpu_env, arg32[1].in,
+ gen_helper_ftoi_s(arg[0].out, tcg_env, arg32[1].in,
rounding_mode, scale);
}
put_f32_i1(arg, arg32, 1);
static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_madd_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_mul_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
}
static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_msub_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_sub_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
}
static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in);
+ gen_helper_wur_fpu2k_fcr(tcg_env, arg[0].in);
}
static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[],
static void translate_add_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_add_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
+ gen_helper_add_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
}
static void translate_add_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_add_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2);
- gen_helper_add_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
+ gen_helper_add_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2);
}
}
TCGv_i32 v = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(v, arg[1].in);
- gen_helper_cvtd_s(arg[0].out, cpu_env, v);
+ gen_helper_cvtd_s(arg[0].out, tcg_env, v);
}
static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[],
{
TCGv_i32 v = tcg_temp_new_i32();
- gen_helper_cvts_d(v, cpu_env, arg[1].in);
+ gen_helper_cvts_d(v, tcg_env, arg[1].in);
tcg_gen_extu_i32_i64(arg[0].out, v);
}
static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_madd_d(arg[0].out, cpu_env,
+ gen_helper_madd_d(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_madd_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
- gen_helper_madd_s(arg32[0].out, cpu_env,
+ gen_helper_madd_s(arg32[0].out, tcg_env,
arg32[0].in, arg32[1].in, arg32[2].in);
put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
}
static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_mul_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
+ gen_helper_mul_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
}
static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_mul_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2);
- gen_helper_mul_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
+ gen_helper_mul_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2);
}
}
static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_msub_d(arg[0].out, cpu_env,
+ gen_helper_msub_d(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_msub_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
- gen_helper_msub_s(arg32[0].out, cpu_env,
+ gen_helper_msub_s(arg32[0].out, tcg_env,
arg32[0].in, arg32[1].in, arg32[2].in);
put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
}
static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_sub_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
+ gen_helper_sub_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
}
static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_sub_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2);
- gen_helper_sub_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
+ gen_helper_sub_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2);
}
}
static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_mkdadj_d(arg[0].out, cpu_env, arg[0].in, arg[1].in);
+ gen_helper_mkdadj_d(arg[0].out, tcg_env, arg[0].in, arg[1].in);
}
static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[],
OpcodeArg arg32[2];
get_f32_o1_i2(arg, arg32, 0, 0, 1);
- gen_helper_mkdadj_s(arg32[0].out, cpu_env, arg32[0].in, arg32[1].in);
+ gen_helper_mkdadj_s(arg32[0].out, tcg_env, arg32[0].in, arg32[1].in);
put_f32_o1_i2(arg, arg32, 0, 0, 1);
}
static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_mksadj_d(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_mksadj_d(arg[0].out, tcg_env, arg[1].in);
}
static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[],
OpcodeArg arg32[2];
get_f32_o1_i1(arg, arg32, 0, 1);
- gen_helper_mksadj_s(arg32[0].out, cpu_env, arg32[1].in);
+ gen_helper_mksadj_s(arg32[0].out, tcg_env, arg32[1].in);
put_f32_o1_i1(arg, arg32, 0, 1);
}
static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wur_fpu_fcr(cpu_env, arg[0].in);
+ gen_helper_wur_fpu_fcr(tcg_env, arg[0].in);
}
static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_rur_fpu_fsr(arg[0].out, cpu_env);
+ gen_helper_rur_fpu_fsr(arg[0].out, tcg_env);
}
static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wur_fpu_fsr(cpu_env, arg[0].in);
+ gen_helper_wur_fpu_fsr(tcg_env, arg[0].in);
}
static const XtensaOpcodeOps fpu_ops[] = {
projects / mirror_qemu.git / blobdiff