#include "exec/log.h"
+#define HELPER_H "helper.h"
+#include "exec/helper-info.c.inc"
+#undef HELPER_H
+
struct DisasContext {
DisasContextBase base;
bool sar_5bit;
bool sar_m32_5bit;
- bool sar_m32_allocated;
TCGv_i32 sar_m32;
unsigned window;
static GHashTable *xtensa_regfile_table;
-#include "exec/gen-icount.h"
-
static char *sr_name[256];
static char *ur_name[256];
};
int i;
- cpu_pc = tcg_global_mem_new_i32(cpu_env,
+ cpu_pc = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, pc), "pc");
for (i = 0; i < 16; i++) {
- cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_R[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, regs[i]),
regnames[i]);
}
for (i = 0; i < 16; i++) {
- cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_FR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
fregs[i].f32[FP_F32_LOW]),
fregnames[i]);
}
for (i = 0; i < 16; i++) {
- cpu_FRD[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_FRD[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUXtensaState,
fregs[i].f64),
fregnames[i]);
}
for (i = 0; i < 4; i++) {
- cpu_MR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_MR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[MR + i]),
mregnames[i]);
}
for (i = 0; i < 16; i++) {
- cpu_BR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_BR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
if (i % 4 == 0) {
- cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env,
+ cpu_BR4[i / 4] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
}
if (i % 8 == 0) {
- cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env,
+ cpu_BR8[i / 8] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
for (i = 0; i < 256; ++i) {
if (sr_name[i]) {
- cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_SR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[i]),
sr_name[i]);
for (i = 0; i < 256; ++i) {
if (ur_name[i]) {
- cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_UR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
uregs[i]),
ur_name[i]);
}
cpu_windowbase_next =
- tcg_global_mem_new_i32(cpu_env,
+ tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, windowbase_next),
"windowbase_next");
cpu_exclusive_addr =
- tcg_global_mem_new_i32(cpu_env,
+ tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, exclusive_addr),
"exclusive_addr");
cpu_exclusive_val =
- tcg_global_mem_new_i32(cpu_env,
+ tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, exclusive_val),
"exclusive_val");
}
{
dc->sar_5bit = false;
dc->sar_m32_5bit = false;
- dc->sar_m32_allocated = false;
-}
-
-static void reset_sar_tracker(DisasContext *dc)
-{
- if (dc->sar_m32_allocated) {
- tcg_temp_free(dc->sar_m32);
- }
+ dc->sar_m32 = NULL;
}
static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
{
- TCGv_i32 tmp = tcg_const_i32(32);
- if (!dc->sar_m32_allocated) {
- dc->sar_m32 = tcg_temp_local_new_i32();
- dc->sar_m32_allocated = true;
+ if (!dc->sar_m32) {
+ dc->sar_m32 = tcg_temp_new_i32();
}
tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
- tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
+ tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32);
dc->sar_5bit = false;
dc->sar_m32_5bit = true;
- tcg_temp_free(tmp);
}
static void gen_exception(DisasContext *dc, int excp)
{
- TCGv_i32 tmp = tcg_const_i32(excp);
- gen_helper_exception(cpu_env, tmp);
- tcg_temp_free(tmp);
+ gen_helper_exception(tcg_env, tcg_constant_i32(excp));
}
static void gen_exception_cause(DisasContext *dc, uint32_t cause)
{
- TCGv_i32 tpc = tcg_const_i32(dc->pc);
- TCGv_i32 tcause = tcg_const_i32(cause);
- gen_helper_exception_cause(cpu_env, tpc, tcause);
- tcg_temp_free(tpc);
- tcg_temp_free(tcause);
+ TCGv_i32 pc = tcg_constant_i32(dc->pc);
+ gen_helper_exception_cause(tcg_env, pc, tcg_constant_i32(cause));
if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) {
dc->base.is_jmp = DISAS_NORETURN;
static void gen_debug_exception(DisasContext *dc, uint32_t cause)
{
- TCGv_i32 tpc = tcg_const_i32(dc->pc);
- TCGv_i32 tcause = tcg_const_i32(cause);
- gen_helper_debug_exception(cpu_env, tpc, tcause);
- tcg_temp_free(tpc);
- tcg_temp_free(tcause);
+ TCGv_i32 pc = tcg_constant_i32(dc->pc);
+ gen_helper_debug_exception(tcg_env, pc, tcg_constant_i32(cause));
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
dc->base.is_jmp = DISAS_NORETURN;
}
if (dc->icount) {
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
}
- if (dc->base.singlestep_enabled) {
- gen_exception(dc, EXCP_DEBUG);
+ if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
+ slot = gen_postprocess(dc, slot);
+ }
+ if (slot >= 0) {
+ tcg_gen_goto_tb(slot);
+ tcg_gen_exit_tb(dc->base.tb, slot);
} else {
- if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
- slot = gen_postprocess(dc, slot);
- }
- if (slot >= 0) {
- tcg_gen_goto_tb(slot);
- tcg_gen_exit_tb(dc->base.tb, slot);
- } else {
- tcg_gen_exit_tb(NULL, 0);
- }
+ tcg_gen_exit_tb(NULL, 0);
}
dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
{
- TCGv_i32 tmp = tcg_const_i32(dest);
- gen_jump_slot(dc, tmp, adjust_jump_slot(dc, dest, slot));
- tcg_temp_free(tmp);
+ gen_jump_slot(dc, tcg_constant_i32(dest),
+ adjust_jump_slot(dc, dest, slot));
}
static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
int slot)
{
- TCGv_i32 tcallinc = tcg_const_i32(callinc);
-
tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
- tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
- tcg_temp_free(tcallinc);
+ tcg_constant_i32(callinc), PS_CALLINC_SHIFT, PS_CALLINC_LEN);
tcg_gen_movi_i32(cpu_R[callinc << 2],
(callinc << 30) | (dc->base.pc_next & 0x3fffffff));
gen_jump_slot(dc, dest, slot);
static void gen_brcondi(DisasContext *dc, TCGCond cond,
TCGv_i32 t0, uint32_t t1, uint32_t addr)
{
- TCGv_i32 tmp = tcg_const_i32(t1);
- gen_brcond(dc, cond, t0, tmp, addr);
- tcg_temp_free(tmp);
+ gen_brcond(dc, cond, t0, tcg_constant_i32(t1), addr);
}
static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[],
return mop;
}
-#ifndef CONFIG_USER_ONLY
-static void gen_waiti(DisasContext *dc, uint32_t imm4)
-{
- TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
- TCGv_i32 intlevel = tcg_const_i32(imm4);
-
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_waiti(cpu_env, pc, intlevel);
- tcg_temp_free(pc);
- tcg_temp_free(intlevel);
-}
-#endif
-
static bool gen_window_check(DisasContext *dc, uint32_t mask)
{
unsigned r = 31 - clz32(mask);
if (r / 4 > dc->window) {
- TCGv_i32 pc = tcg_const_i32(dc->pc);
- TCGv_i32 w = tcg_const_i32(r / 4);
+ TCGv_i32 pc = tcg_constant_i32(dc->pc);
+ TCGv_i32 w = tcg_constant_i32(r / 4);
- gen_helper_window_check(cpu_env, pc, w);
+ gen_helper_window_check(tcg_env, pc, w);
dc->base.is_jmp = DISAS_NORETURN;
return false;
}
#ifndef CONFIG_USER_ONLY
if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_check_interrupts(cpu_env);
+ translator_io_start(&dc->base);
+ gen_helper_check_interrupts(tcg_env);
}
#endif
if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
- gen_helper_sync_windowbase(cpu_env);
+ gen_helper_sync_windowbase(tcg_env);
}
if (op_flags & XTENSA_OP_EXIT_TB_M1) {
slot = -1;
}
if (op_flags & XTENSA_OP_UNDERFLOW) {
- TCGv_i32 tmp = tcg_const_i32(dc->pc);
+ TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_test_underflow_retw(cpu_env, tmp);
- tcg_temp_free(tmp);
+ gen_helper_test_underflow_retw(tcg_env, pc);
}
if (op_flags & XTENSA_OP_ALLOCA) {
- TCGv_i32 tmp = tcg_const_i32(dc->pc);
+ TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_movsp(cpu_env, tmp);
- tcg_temp_free(tmp);
+ gen_helper_movsp(tcg_env, pc);
}
if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
if (i == 0 || arg_copy[i].resource != resource) {
resource = arg_copy[i].resource;
if (arg_copy[i].arg->num_bits <= 32) {
- temp = tcg_temp_local_new_i32();
+ temp = tcg_temp_new_i32();
tcg_gen_mov_i32(temp, arg_copy[i].arg->in);
} else if (arg_copy[i].arg->num_bits <= 64) {
- temp = tcg_temp_local_new_i64();
+ temp = tcg_temp_new_i64();
tcg_gen_mov_i64(temp, arg_copy[i].arg->in);
} else {
g_assert_not_reached();
ops->translate(dc, pslot->arg, ops->par);
}
- for (i = 0; i < n_arg_copy; ++i) {
- if (arg_copy[i].arg->num_bits <= 32) {
- tcg_temp_free_i32(arg_copy[i].temp);
- } else if (arg_copy[i].arg->num_bits <= 64) {
- tcg_temp_free_i64(arg_copy[i].temp);
- } else {
- g_assert_not_reached();
- }
- }
-
if (dc->base.is_jmp == DISAS_NEXT) {
gen_postprocess(dc, 0);
dc->op_flags = 0;
return xtensa_op0_insn_len(dc, b0);
}
-static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
-{
- unsigned i;
-
- for (i = 0; i < dc->config->nibreak; ++i) {
- if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
- env->sregs[IBREAKA + i] == dc->pc) {
- gen_debug_exception(dc, DEBUGCAUSE_IB);
- break;
- }
- }
-}
-
static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUXtensaState *env = cpu->env_ptr;
+ CPUXtensaState *env = cpu_env(cpu);
uint32_t tb_flags = dc->base.tb->flags;
dc->config = env->config;
DisasContext *dc = container_of(dcbase, DisasContext, base);
if (dc->icount) {
- dc->next_icount = tcg_temp_local_new_i32();
+ dc->next_icount = tcg_temp_new_i32();
}
}
static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUXtensaState *env = cpu->env_ptr;
+ CPUXtensaState *env = cpu_env(cpu);
target_ulong page_start;
/* These two conditions only apply to the first insn in the TB,
gen_set_label(label);
}
- if (dc->debug) {
- gen_ibreak_check(env, dc);
- }
-
disas_xtensa_insn(env, dc);
if (dc->icount) {
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- reset_sar_tracker(dc);
- if (dc->icount) {
- tcg_temp_free(dc->next_icount);
- }
-
switch (dc->base.is_jmp) {
case DISAS_NORETURN:
break;
case DISAS_TOO_MANY:
- if (dc->base.singlestep_enabled) {
- tcg_gen_movi_i32(cpu_pc, dc->pc);
- gen_exception(dc, EXCP_DEBUG);
- } else {
- gen_jumpi(dc, dc->pc, 0);
- }
+ gen_jumpi(dc, dc->pc, 0);
break;
default:
g_assert_not_reached();
}
}
-static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
+static void xtensa_tr_disas_log(const DisasContextBase *dcbase,
+ CPUState *cpu, FILE *logfile)
{
- qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
- log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
+ fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
+ target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
}
static const TranslatorOps xtensa_translator_ops = {
.disas_log = xtensa_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
+ vaddr pc, void *host_pc)
{
DisasContext dc = {};
- translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb, max_insns);
+ translator_loop(cpu, tb, max_insns, pc, host_pc,
+ &xtensa_translator_ops, &dc.base);
}
void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
-void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- env->pc = data[0];
-}
-
static void translate_abs(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_shli_i32(tmp, arg[1].in, par[0]);
tcg_gen_add_i32(arg[0].out, tmp, arg[2].in);
- tcg_temp_free(tmp);
}
static void translate_all(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
uint32_t shift = par[1];
- TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1].imm);
+ TCGv_i32 mask = tcg_constant_i32(((1 << shift) - 1) << arg[1].imm);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_and_i32(tmp, arg[1].in, mask);
tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift);
tcg_gen_deposit_i32(arg[0].out, arg[0].out,
tmp, arg[0].imm, 1);
- tcg_temp_free(mask);
- tcg_temp_free(tmp);
}
static void translate_and(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_and_i32(tmp, arg[0].in, arg[1].in);
gen_brcond(dc, par[0], tmp, arg[1].in, arg[2].imm);
- tcg_temp_free(tmp);
}
static void translate_bany(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_and_i32(tmp, arg[0].in, arg[1].in);
gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
- tcg_temp_free(tmp);
}
static void translate_b(DisasContext *dc, const OpcodeArg arg[],
static void translate_bb(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-#ifdef TARGET_WORDS_BIGENDIAN
- TCGv_i32 bit = tcg_const_i32(0x80000000u);
-#else
- TCGv_i32 bit = tcg_const_i32(0x00000001u);
-#endif
TCGv_i32 tmp = tcg_temp_new_i32();
+
tcg_gen_andi_i32(tmp, arg[1].in, 0x1f);
-#ifdef TARGET_WORDS_BIGENDIAN
- tcg_gen_shr_i32(bit, bit, tmp);
-#else
- tcg_gen_shl_i32(bit, bit, tmp);
-#endif
- tcg_gen_and_i32(tmp, arg[0].in, bit);
+ if (TARGET_BIG_ENDIAN) {
+ tcg_gen_shr_i32(tmp, tcg_constant_i32(0x80000000u), tmp);
+ } else {
+ tcg_gen_shl_i32(tmp, tcg_constant_i32(0x00000001u), tmp);
+ }
+ tcg_gen_and_i32(tmp, arg[0].in, tmp);
gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
- tcg_temp_free(tmp);
- tcg_temp_free(bit);
}
static void translate_bbi(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 tmp = tcg_temp_new_i32();
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm);
#else
tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm);
#endif
gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
- tcg_temp_free(tmp);
}
static void translate_bi(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm);
op[par[0]](tmp1, tmp1, tmp2);
tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1);
- tcg_temp_free(tmp1);
- tcg_temp_free(tmp2);
}
static void translate_bp(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm);
gen_brcondi(dc, par[0], tmp, 0, arg[1].imm);
- tcg_temp_free(tmp);
}
static void translate_call0(DisasContext *dc, const OpcodeArg arg[],
static void translate_callw(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
+ TCGv_i32 tmp = tcg_constant_i32(arg[0].imm);
gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0].imm, 0));
- tcg_temp_free(tmp);
}
static void translate_callx0(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_mov_i32(tmp, arg[0].in);
tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
gen_jump(dc, tmp);
- tcg_temp_free(tmp);
}
static void translate_callxw(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_mov_i32(tmp, arg[0].in);
gen_callw_slot(dc, par[0], tmp, -1);
- tcg_temp_free(tmp);
}
static void translate_clamps(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2].imm);
- TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2].imm) - 1);
+ TCGv_i32 tmp1 = tcg_constant_i32(-1u << arg[2].imm);
+ TCGv_i32 tmp2 = tcg_constant_i32((1 << arg[2].imm) - 1);
- tcg_gen_smax_i32(tmp1, tmp1, arg[1].in);
- tcg_gen_smin_i32(arg[0].out, tmp1, tmp2);
- tcg_temp_free(tmp1);
- tcg_temp_free(tmp2);
+ tcg_gen_smax_i32(arg[0].out, tmp1, arg[1].in);
+ tcg_gen_smin_i32(arg[0].out, arg[0].out, tmp2);
}
static void translate_clrb_expstate(DisasContext *dc, const OpcodeArg arg[],
static void translate_const16(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 c = tcg_const_i32(arg[1].imm);
+ TCGv_i32 c = tcg_constant_i32(arg[1].imm);
tcg_gen_deposit_i32(arg[0].out, c, arg[0].in, 16, 16);
- tcg_temp_free(c);
}
static void translate_dcache(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 res = tcg_temp_new_i32();
tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
- tcg_gen_qemu_ld8u(res, addr, dc->cring);
- tcg_temp_free(addr);
- tcg_temp_free(res);
+ tcg_gen_qemu_ld_i32(res, addr, dc->cring, MO_UB);
}
static void translate_depbits(DisasContext *dc, const OpcodeArg arg[],
static void translate_entry(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 pc = tcg_const_i32(dc->pc);
- TCGv_i32 s = tcg_const_i32(arg[0].imm);
- TCGv_i32 imm = tcg_const_i32(arg[1].imm);
- gen_helper_entry(cpu_env, pc, s, imm);
- tcg_temp_free(imm);
- tcg_temp_free(s);
- tcg_temp_free(pc);
+ TCGv_i32 pc = tcg_constant_i32(dc->pc);
+ TCGv_i32 s = tcg_constant_i32(arg[0].imm);
+ TCGv_i32 imm = tcg_constant_i32(arg[1].imm);
+ gen_helper_entry(tcg_env, pc, s, imm);
}
static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_shri_i32(tmp, arg[1].in, arg[2].imm);
tcg_gen_andi_i32(arg[0].out, tmp, maskimm);
- tcg_temp_free(tmp);
}
static void translate_getex(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_extract_i32(tmp, cpu_SR[ATOMCTL], 8, 1);
tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], arg[0].in, 8, 1);
tcg_gen_mov_i32(arg[0].out, tmp);
- tcg_temp_free(tmp);
}
static void translate_icache(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_movi_i32(cpu_pc, dc->pc);
tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
- gen_helper_itlb_hit_test(cpu_env, addr);
- tcg_temp_free(addr);
+ gen_helper_itlb_hit_test(tcg_env, addr);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- TCGv_i32 dtlb = tcg_const_i32(par[0]);
+ TCGv_i32 dtlb = tcg_constant_i32(par[0]);
- gen_helper_itlb(cpu_env, arg[0].in, dtlb);
- tcg_temp_free(dtlb);
+ gen_helper_itlb(tcg_env, arg[0].in, dtlb);
#endif
}
tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
mop = gen_load_store_alignment(dc, MO_TEUL, addr);
tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, mop);
- tcg_temp_free(addr);
}
#ifdef CONFIG_USER_ONLY
static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write)
{
if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
- TCGv_i32 tpc = tcg_const_i32(dc->pc);
- TCGv_i32 write = tcg_const_i32(is_write);
+ TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_check_exclusive(cpu_env, tpc, addr, write);
- tcg_temp_free(tpc);
- tcg_temp_free(write);
+ gen_helper_check_exclusive(tcg_env, pc, addr,
+ tcg_constant_i32(is_write));
}
}
#endif
tcg_gen_qemu_ld_i32(arg[0].out, addr, dc->cring, mop);
tcg_gen_mov_i32(cpu_exclusive_addr, addr);
tcg_gen_mov_i32(cpu_exclusive_val, arg[0].out);
- tcg_temp_free(addr);
}
static void translate_ldst(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL);
}
}
- tcg_temp_free(addr);
+}
+
+static void translate_lct(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
+{
+ tcg_gen_movi_i32(arg[0].out, 0);
}
static void translate_l32r(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 tmp;
if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) {
- tmp = tcg_const_i32(arg[1].raw_imm - 1);
- tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
+ tmp = tcg_temp_new();
+ tcg_gen_addi_i32(tmp, cpu_SR[LITBASE], arg[1].raw_imm - 1);
} else {
- tmp = tcg_const_i32(arg[1].imm);
+ tmp = tcg_constant_i32(arg[1].imm);
}
- tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring);
- tcg_temp_free(tmp);
+ tcg_gen_qemu_ld_i32(arg[0].out, tmp, dc->cring, MO_TEUL);
}
static void translate_loop(DisasContext *dc, const OpcodeArg arg[],
lo, hi);
}
tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
-
- tcg_temp_free_i32(lo);
- tcg_temp_free_i32(hi);
}
- tcg_temp_free(m1);
- tcg_temp_free(m2);
}
if (ld_offset) {
tcg_gen_mov_i32(arg[1].out, vaddr);
tcg_gen_mov_i32(cpu_SR[MR + arg[0].imm], mem32);
}
- tcg_temp_free(vaddr);
- tcg_temp_free(mem32);
}
static void translate_memw(DisasContext *dc, const OpcodeArg arg[],
static void translate_movcond(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero, arg[1].in, arg[0].in);
- tcg_temp_free(zero);
}
static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
tcg_gen_movcond_i32(par[0],
arg[0].out, tmp, zero,
arg[1].in, arg[0].in);
- tcg_temp_free(tmp);
- tcg_temp_free(zero);
}
static void translate_movsp(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_ext16u_i32(v2, arg[2].in);
}
tcg_gen_mul_i32(arg[0].out, v1, v2);
- tcg_temp_free(v2);
- tcg_temp_free(v1);
}
static void translate_mull(DisasContext *dc, const OpcodeArg arg[],
} else {
tcg_gen_mulu2_i32(lo, arg[0].out, arg[1].in, arg[2].in);
}
- tcg_temp_free(lo);
}
static void translate_neg(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- TCGv_i32 dtlb = tcg_const_i32(par[0]);
+ TCGv_i32 dtlb = tcg_constant_i32(par[0]);
tcg_gen_movi_i32(cpu_pc, dc->pc);
- gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
- tcg_temp_free(dtlb);
+ gen_helper_ptlb(arg[0].out, tcg_env, arg[1].in, dtlb);
#endif
}
{
#ifndef CONFIG_USER_ONLY
tcg_gen_movi_i32(cpu_pc, dc->pc);
- gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_pptlb(arg[0].out, tcg_env, arg[1].in);
#endif
}
static void translate_rer(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_rer(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_rer(arg[0].out, tcg_env, arg[1].in);
}
static void translate_ret(DisasContext *dc, const OpcodeArg arg[],
"Illegal retw instruction(pc = %08x)\n", dc->pc);
return XTENSA_OP_ILL;
} else {
- TCGv_i32 tmp = tcg_const_i32(dc->pc);
+ TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_test_ill_retw(cpu_env, tmp);
- tcg_temp_free(tmp);
+ gen_helper_test_ill_retw(tcg_env, pc);
return 0;
}
}
static void translate_retw(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp = tcg_const_i32(1);
- tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
+ TCGv_i32 tmp = tcg_temp_new();
+ tcg_gen_shl_i32(tmp, tcg_constant_i32(1), cpu_SR[WINDOW_BASE]);
tcg_gen_andc_i32(cpu_SR[WINDOW_START],
cpu_SR[WINDOW_START], tmp);
tcg_gen_movi_i32(tmp, dc->pc);
tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30);
- gen_helper_retw(cpu_env, cpu_R[0]);
+ gen_helper_retw(tcg_env, cpu_R[0]);
gen_jump(dc, tmp);
- tcg_temp_free(tmp);
}
static void translate_rfde(DisasContext *dc, const OpcodeArg arg[],
static void translate_rfw(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp = tcg_const_i32(1);
+ TCGv_i32 tmp = tcg_temp_new();
tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
- tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
+ tcg_gen_shl_i32(tmp, tcg_constant_i32(1), cpu_SR[WINDOW_BASE]);
if (par[0]) {
tcg_gen_andc_i32(cpu_SR[WINDOW_START],
cpu_SR[WINDOW_START], tmp);
}
- tcg_temp_free(tmp);
- gen_helper_restore_owb(cpu_env);
+ gen_helper_restore_owb(tcg_env);
gen_jump(dc, cpu_SR[EPC1]);
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_update_ccount(cpu_env);
+ translator_io_start(&dc->base);
+ gen_helper_update_ccount(tcg_env);
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
#endif
}
tcg_gen_shri_i32(tmp, cpu_SR[EXCVADDR], 10);
tcg_gen_or_i32(tmp, tmp, cpu_SR[PTEVADDR]);
tcg_gen_andi_i32(arg[0].out, tmp, 0xfffffffc);
- tcg_temp_free(tmp);
#endif
}
gen_helper_rtlb0,
gen_helper_rtlb1,
};
- TCGv_i32 dtlb = tcg_const_i32(par[0]);
+ TCGv_i32 dtlb = tcg_constant_i32(par[0]);
- helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
- tcg_temp_free(dtlb);
+ helper[par[1]](arg[0].out, tcg_env, arg[1].in, dtlb);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_rptlb0(arg[0].out, tcg_env, arg[1].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_rptlb1(arg[0].out, tcg_env, arg[1].in);
#endif
}
#else
static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
{
- TCGv_i32 tpc = tcg_const_i32(dc->pc);
+ TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_check_atomctl(cpu_env, tpc, addr);
- tcg_temp_free(tpc);
+ gen_helper_check_atomctl(tcg_env, pc, addr);
}
#endif
static void translate_s32c1i(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp = tcg_temp_local_new_i32();
- TCGv_i32 addr = tcg_temp_local_new_i32();
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ TCGv_i32 addr = tcg_temp_new_i32();
MemOp mop;
tcg_gen_mov_i32(tmp, arg[0].in);
gen_check_atomctl(dc, addr);
tcg_gen_atomic_cmpxchg_i32(arg[0].out, addr, cpu_SR[SCOMPARE1],
tmp, dc->cring, mop);
- tcg_temp_free(addr);
- tcg_temp_free(tmp);
}
static void translate_s32e(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
mop = gen_load_store_alignment(dc, MO_TEUL, addr);
tcg_gen_qemu_st_tl(arg[0].in, addr, dc->ring, mop);
- tcg_temp_free(addr);
}
static void translate_s32ex(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 prev = tcg_temp_new_i32();
- TCGv_i32 addr = tcg_temp_local_new_i32();
- TCGv_i32 res = tcg_temp_local_new_i32();
+ TCGv_i32 addr = tcg_temp_new_i32();
+ TCGv_i32 res = tcg_temp_new_i32();
TCGLabel *label = gen_new_label();
MemOp mop;
gen_set_label(label);
tcg_gen_extract_i32(arg[0].out, cpu_SR[ATOMCTL], 8, 1);
tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], res, 8, 1);
- tcg_temp_free(prev);
- tcg_temp_free(addr);
- tcg_temp_free(res);
}
static void translate_salt(DisasContext *dc, const OpcodeArg arg[],
static void translate_sext(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- int shift = 31 - arg[2].imm;
-
- if (shift == 24) {
- tcg_gen_ext8s_i32(arg[0].out, arg[1].in);
- } else if (shift == 16) {
- tcg_gen_ext16s_i32(arg[0].out, arg[1].in);
- } else {
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_shli_i32(tmp, arg[1].in, shift);
- tcg_gen_sari_i32(arg[0].out, tmp, shift);
- tcg_temp_free(tmp);
- }
+ tcg_gen_sextract_i32(arg[0].out, arg[1].in, 0, arg[2].imm + 1);
}
static uint32_t test_exceptions_simcall(DisasContext *dc,
const OpcodeArg arg[],
const uint32_t par[])
{
+ bool is_semi = semihosting_enabled(dc->cring != 0);
#ifdef CONFIG_USER_ONLY
bool ill = true;
#else
/* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
- bool ill = dc->config->hw_version <= 250002 && !semihosting_enabled();
+ bool ill = dc->config->hw_version <= 250002 && !is_semi;
#endif
- if (ill || !semihosting_enabled()) {
+ if (ill || !is_semi) {
qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
}
return ill ? XTENSA_OP_ILL : 0;
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- if (semihosting_enabled()) {
- gen_helper_simcall(cpu_env);
+ if (semihosting_enabled(dc->cring != 0)) {
+ gen_helper_simcall(tcg_env);
}
#endif
}
tcg_gen_extu_i32_i64(tmp, reg); \
tcg_gen_##cmd##_i64(v, v, tmp); \
tcg_gen_extrl_i64_i32(arg[0].out, v); \
- tcg_temp_free_i64(v); \
- tcg_temp_free_i64(tmp); \
} while (0)
#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
tcg_gen_shl_i32(arg[0].out, arg[1].in, dc->sar_m32);
} else {
TCGv_i64 v = tcg_temp_new_i64();
- TCGv_i32 s = tcg_const_i32(32);
- tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
+ TCGv_i32 s = tcg_temp_new();
+ tcg_gen_subfi_i32(s, 32, cpu_SR[SAR]);
tcg_gen_andi_i32(s, s, 0x3f);
tcg_gen_extu_i32_i64(v, arg[1].in);
gen_shift_reg(shl, s);
- tcg_temp_free(s);
}
}
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_shli_i32(tmp, arg[0].in, 3);
gen_left_shift_sar(dc, tmp);
- tcg_temp_free(tmp);
}
static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_shli_i32(tmp, arg[0].in, 3);
gen_right_shift_sar(dc, tmp);
- tcg_temp_free(tmp);
}
static void translate_ssai(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
- gen_right_shift_sar(dc, tmp);
- tcg_temp_free(tmp);
+ gen_right_shift_sar(dc, tcg_constant_i32(arg[0].imm));
}
static void translate_ssl(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_shli_i32(tmp, arg[1].in, par[0]);
tcg_gen_sub_i32(arg[0].out, tmp, arg[2].in);
- tcg_temp_free(tmp);
}
static void translate_waiti(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_waiti(dc, arg[0].imm);
+ TCGv_i32 pc = tcg_constant_i32(dc->base.pc_next);
+
+ translator_io_start(&dc->base);
+ gen_helper_waiti(tcg_env, pc, tcg_constant_i32(arg[0].imm));
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- TCGv_i32 dtlb = tcg_const_i32(par[0]);
+ TCGv_i32 dtlb = tcg_constant_i32(par[0]);
- gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
- tcg_temp_free(dtlb);
+ gen_helper_wtlb(tcg_env, arg[0].in, arg[1].in, dtlb);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in);
+ gen_helper_wptlb(tcg_env, arg[0].in, arg[1].in);
#endif
}
static void translate_wer(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wer(cpu_env, arg[0].in, arg[1].in);
+ gen_helper_wer(tcg_env, arg[0].in, arg[1].in);
}
static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
uint32_t id = par[0] - CCOMPARE;
- TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nccompare);
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ translator_io_start(&dc->base);
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
- gen_helper_update_ccompare(cpu_env, tmp);
- tcg_temp_free(tmp);
+ gen_helper_update_ccompare(tcg_env, tcg_constant_i32(id));
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_wsr_ccount(cpu_env, arg[0].in);
+ translator_io_start(&dc->base);
+ gen_helper_wsr_ccount(tcg_env, arg[0].in);
#endif
}
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - DBREAKA;
- TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
- gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
- tcg_temp_free(tmp);
+ gen_helper_wsr_dbreaka(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif
}
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - DBREAKC;
- TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
- gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
- tcg_temp_free(tmp);
+ gen_helper_wsr_dbreakc(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif
}
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - IBREAKA;
- TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nibreak);
- gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
- tcg_temp_free(tmp);
+ gen_helper_wsr_ibreaka(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_ibreakenable(cpu_env, arg[0].in);
+ gen_helper_wsr_ibreakenable(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_intclear(cpu_env, arg[0].in);
+ gen_helper_intclear(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_intset(cpu_env, arg[0].in);
+ gen_helper_intset(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_memctl(cpu_env, arg[0].in);
+ gen_helper_wsr_memctl(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_mpuenb(cpu_env, arg[0].in);
+ gen_helper_wsr_mpuenb(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_rasid(cpu_env, arg[0].in);
+ gen_helper_wsr_rasid(tcg_env, arg[0].in);
#endif
}
tcg_gen_mov_i32(tmp, arg[0].in);
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
- tcg_temp_free(tmp);
} else {
tcg_gen_movi_i32(arg[0].out, 0);
}
tcg_gen_mov_i32(tmp, arg[0].in);
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
- tcg_temp_free(tmp);
} else {
tcg_gen_movi_i32(arg[0].out, 0);
}
#ifndef CONFIG_USER_ONLY
TCGv_i32 tmp = tcg_temp_new_i32();
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
-
- gen_helper_update_ccount(cpu_env);
+ translator_io_start(&dc->base);
+ gen_helper_update_ccount(tcg_env);
tcg_gen_mov_i32(tmp, cpu_SR[par[0]]);
- gen_helper_wsr_ccount(cpu_env, arg[0].in);
+ gen_helper_wsr_ccount(tcg_env, arg[0].in);
tcg_gen_mov_i32(arg[0].out, tmp);
- tcg_temp_free(tmp);
#endif
}
} \
translate_wsr_##name(dc, arg, par); \
tcg_gen_mov_i32(arg[0].out, tmp); \
- tcg_temp_free(tmp); \
}
gen_translate_xsr(acchi)
.translate = translate_ldst,
.par = (const uint32_t[]){MO_UB, false, false},
.op_flags = XTENSA_OP_LOAD,
+ }, {
+ .name = "ldct",
+ .translate = translate_lct,
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "ldcw",
+ .translate = translate_nop,
+ .op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "lddec",
.translate = translate_mac16,
}, {
.name = "ldpte",
.op_flags = XTENSA_OP_ILL,
+ }, {
+ .name = "lict",
+ .translate = translate_lct,
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "licw",
+ .translate = translate_nop,
+ .op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = (const char * const[]) {
"loop", "loop.w15", NULL,
.name = "saltu",
.translate = translate_salt,
.par = (const uint32_t[]){TCG_COND_LTU},
+ }, {
+ .name = "sdct",
+ .translate = translate_nop,
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "sdcw",
+ .translate = translate_nop,
+ .op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "setb_expstate",
.translate = translate_setb_expstate,
}, {
.name = "sext",
.translate = translate_sext,
+ }, {
+ .name = "sict",
+ .translate = translate_nop,
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "sicw",
+ .translate = translate_nop,
+ .op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "simcall",
.translate = translate_simcall,
(o0 >= 0 && arg[o0].num_bits == 64)) {
if (o0 >= 0) {
tcg_gen_extu_i32_i64(arg[o0].out, arg32[o0].out);
- tcg_temp_free_i32(arg32[o0].out);
- }
- if (i0 >= 0) {
- tcg_temp_free_i32(arg32[i0].in);
- }
- if (i1 >= 0) {
- tcg_temp_free_i32(arg32[i1].in);
- }
- if (i2 >= 0) {
- tcg_temp_free_i32(arg32[i2].in);
}
}
}
static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_add_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
}
[COMPARE_OLE] = gen_helper_ole_d,
[COMPARE_ULE] = gen_helper_ule_d,
};
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm);
tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
- helper[par[0]](res, cpu_env, arg[1].in, arg[2].in);
+ helper[par[0]](res, tcg_env, arg[1].in, arg[2].in);
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
- tcg_temp_free(zero);
- tcg_temp_free(res);
- tcg_temp_free(set_br);
- tcg_temp_free(clr_br);
}
static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[],
[COMPARE_ULE] = gen_helper_ule_s,
};
OpcodeArg arg32[3];
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
get_f32_i2(arg, arg32, 1, 2);
- helper[par[0]](res, cpu_env, arg32[1].in, arg32[2].in);
+ helper[par[0]](res, tcg_env, arg32[1].in, arg32[2].in);
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
put_f32_i2(arg, arg32, 1, 2);
- tcg_temp_free(zero);
- tcg_temp_free(res);
- tcg_temp_free(set_br);
- tcg_temp_free(clr_br);
}
static void translate_const_d(DisasContext *dc, const OpcodeArg arg[],
static void translate_float_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
+ TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
if (par[0]) {
- gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_uitof_d(arg[0].out, tcg_env, arg[1].in, scale);
} else {
- gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_itof_d(arg[0].out, tcg_env, arg[1].in, scale);
}
- tcg_temp_free(scale);
}
static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
+ TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
OpcodeArg arg32[1];
get_f32_o1(arg, arg32, 0);
if (par[0]) {
- gen_helper_uitof_s(arg32[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_uitof_s(arg32[0].out, tcg_env, arg[1].in, scale);
} else {
- gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_itof_s(arg32[0].out, tcg_env, arg[1].in, scale);
}
put_f32_o1(arg, arg32, 0);
- tcg_temp_free(scale);
}
static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
- TCGv_i32 scale = tcg_const_i32(arg[2].imm);
+ TCGv_i32 rounding_mode = tcg_constant_i32(par[0]);
+ TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
if (par[1]) {
- gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in,
+ gen_helper_ftoui_d(arg[0].out, tcg_env, arg[1].in,
rounding_mode, scale);
} else {
- gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in,
+ gen_helper_ftoi_d(arg[0].out, tcg_env, arg[1].in,
rounding_mode, scale);
}
- tcg_temp_free(rounding_mode);
- tcg_temp_free(scale);
}
static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
- TCGv_i32 scale = tcg_const_i32(arg[2].imm);
+ TCGv_i32 rounding_mode = tcg_constant_i32(par[0]);
+ TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
OpcodeArg arg32[2];
get_f32_i1(arg, arg32, 1);
if (par[1]) {
- gen_helper_ftoui_s(arg[0].out, cpu_env, arg32[1].in,
+ gen_helper_ftoui_s(arg[0].out, tcg_env, arg32[1].in,
rounding_mode, scale);
} else {
- gen_helper_ftoi_s(arg[0].out, cpu_env, arg32[1].in,
+ gen_helper_ftoi_s(arg[0].out, tcg_env, arg32[1].in,
rounding_mode, scale);
}
put_f32_i1(arg, arg32, 1);
- tcg_temp_free(rounding_mode);
- tcg_temp_free(scale);
}
static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[],
if (par[1]) {
tcg_gen_mov_i32(arg[1].out, addr);
}
- tcg_temp_free(addr);
}
static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[],
if (par[1]) {
tcg_gen_mov_i32(arg[1].out, addr);
}
- tcg_temp_free(addr);
}
static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_madd_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i64 arg2 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(arg2, arg[2].in);
tcg_gen_movcond_i64(par[0], arg[0].out,
arg2, zero,
arg[1].in, arg[0].in);
- tcg_temp_free_i64(zero);
- tcg_temp_free_i64(arg2);
}
static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (arg[0].num_bits == 32) {
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero,
arg[1].in, arg[0].in);
- tcg_temp_free(zero);
} else {
translate_movcond_d(dc, arg, par);
}
static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i32 tmp1 = tcg_temp_new_i32();
TCGv_i64 tmp2 = tcg_temp_new_i64();
tcg_gen_movcond_i64(par[0],
arg[0].out, tmp2, zero,
arg[1].in, arg[0].in);
- tcg_temp_free_i64(zero);
- tcg_temp_free_i32(tmp1);
- tcg_temp_free_i64(tmp2);
}
static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (arg[0].num_bits == 32) {
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
tcg_gen_movcond_i32(par[0],
arg[0].out, tmp, zero,
arg[1].in, arg[0].in);
- tcg_temp_free(tmp);
- tcg_temp_free(zero);
} else {
translate_movp_d(dc, arg, par);
}
static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_mul_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
}
static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_msub_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_sub_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
}
static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in);
+ gen_helper_wur_fpu2k_fcr(tcg_env, arg[0].in);
}
static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[],
static void translate_add_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_add_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
+ gen_helper_add_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
}
static void translate_add_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_add_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2);
- gen_helper_add_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
+ gen_helper_add_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2);
}
}
TCGv_i32 v = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(v, arg[1].in);
- gen_helper_cvtd_s(arg[0].out, cpu_env, v);
- tcg_temp_free_i32(v);
+ gen_helper_cvtd_s(arg[0].out, tcg_env, v);
}
static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[],
{
TCGv_i32 v = tcg_temp_new_i32();
- gen_helper_cvts_d(v, cpu_env, arg[1].in);
+ gen_helper_cvts_d(v, tcg_env, arg[1].in);
tcg_gen_extu_i32_i64(arg[0].out, v);
- tcg_temp_free_i32(v);
}
static void translate_ldsti_d(DisasContext *dc, const OpcodeArg arg[],
} else {
addr = arg[1].in;
}
- mop = gen_load_store_alignment(dc, MO_TEQ, addr);
+ mop = gen_load_store_alignment(dc, MO_TEUQ, addr);
if (par[0]) {
tcg_gen_qemu_st_i64(arg[0].in, addr, dc->cring, mop);
} else {
tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm);
}
}
- if (par[1]) {
- tcg_temp_free(addr);
- }
}
static void translate_ldsti_s(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm);
}
}
- if (par[1]) {
- tcg_temp_free(addr);
- }
}
static void translate_ldstx_d(DisasContext *dc, const OpcodeArg arg[],
} else {
addr = arg[1].in;
}
- mop = gen_load_store_alignment(dc, MO_TEQ, addr);
+ mop = gen_load_store_alignment(dc, MO_TEUQ, addr);
if (par[0]) {
tcg_gen_qemu_st_i64(arg[0].in, addr, dc->cring, mop);
} else {
tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in);
}
}
- if (par[1]) {
- tcg_temp_free(addr);
- }
}
static void translate_ldstx_s(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in);
}
}
- if (par[1]) {
- tcg_temp_free(addr);
- }
}
static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_madd_d(arg[0].out, cpu_env,
+ gen_helper_madd_d(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_madd_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
- gen_helper_madd_s(arg32[0].out, cpu_env,
+ gen_helper_madd_s(arg32[0].out, tcg_env,
arg32[0].in, arg32[1].in, arg32[2].in);
put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
}
static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_mul_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
+ gen_helper_mul_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
}
static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_mul_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2);
- gen_helper_mul_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
+ gen_helper_mul_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2);
}
}
static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_msub_d(arg[0].out, cpu_env,
+ gen_helper_msub_d(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_msub_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
- gen_helper_msub_s(arg32[0].out, cpu_env,
+ gen_helper_msub_s(arg32[0].out, tcg_env,
arg32[0].in, arg32[1].in, arg32[2].in);
put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
}
static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_sub_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
+ gen_helper_sub_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
}
static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_sub_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2);
- gen_helper_sub_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
+ gen_helper_sub_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2);
}
}
static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_mkdadj_d(arg[0].out, cpu_env, arg[0].in, arg[1].in);
+ gen_helper_mkdadj_d(arg[0].out, tcg_env, arg[0].in, arg[1].in);
}
static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[],
OpcodeArg arg32[2];
get_f32_o1_i2(arg, arg32, 0, 0, 1);
- gen_helper_mkdadj_s(arg32[0].out, cpu_env, arg32[0].in, arg32[1].in);
+ gen_helper_mkdadj_s(arg32[0].out, tcg_env, arg32[0].in, arg32[1].in);
put_f32_o1_i2(arg, arg32, 0, 0, 1);
}
static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_mksadj_d(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_mksadj_d(arg[0].out, tcg_env, arg[1].in);
}
static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[],
OpcodeArg arg32[2];
get_f32_o1_i1(arg, arg32, 0, 1);
- gen_helper_mksadj_s(arg32[0].out, cpu_env, arg32[1].in);
+ gen_helper_mksadj_s(arg32[0].out, tcg_env, arg32[1].in);
put_f32_o1_i1(arg, arg32, 0, 1);
}
static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wur_fpu_fcr(cpu_env, arg[0].in);
+ gen_helper_wur_fpu_fcr(tcg_env, arg[0].in);
}
static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_rur_fpu_fsr(arg[0].out, cpu_env);
+ gen_helper_rur_fpu_fsr(arg[0].out, tcg_env);
}
static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wur_fpu_fsr(cpu_env, arg[0].in);
+ gen_helper_wur_fpu_fsr(tcg_env, arg[0].in);
}
static const XtensaOpcodeOps fpu_ops[] = {
projects / mirror_qemu.git / blobdiff