find -type f | xargs sed -i 's/[\t ]$//g' # on most files

[mirror_qemu.git] / target-i386 / cpu.h

diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 450dd8cbe430fa9ae347699f37af4eb345581485..6cf2c487b843b077381ef2e9e2e739c99f3796b9 100644 (file)
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1,6 +1,6 @@
 /*
  * i386 virtual CPU header
- * 
+ *
  *  Copyright (c) 2003 Fabrice Bellard
  *
  * This library is free software; you can redistribute it and/or
@@ -36,11 +36,17 @@
 
 #define TARGET_HAS_ICE 1
 
+#ifdef TARGET_X86_64
+#define ELF_MACHINE    EM_X86_64
+#else
+#define ELF_MACHINE    EM_386
+#endif
+
 #include "cpu-defs.h"
 
 #include "softfloat.h"
 
-#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
+#if defined(__i386__) && !defined(CONFIG_SOFTMMU) && !defined(__APPLE__)
 #define USE_CODE_COPY
 #endif
 
@@ -110,12 +116,12 @@
 #define NT_MASK                        0x00004000
 #define RF_MASK                        0x00010000
 #define VM_MASK                        0x00020000
-#define AC_MASK                        0x00040000 
+#define AC_MASK                        0x00040000
 #define VIF_MASK                0x00080000
 #define VIP_MASK                0x00100000
 #define ID_MASK                 0x00200000
 
-/* hidden flags - used internally by qemu to represent additionnal cpu
+/* hidden flags - used internally by qemu to represent additional cpu
    states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
    using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
    with eflags. */
@@ -142,6 +148,7 @@
 #define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
 #define HF_VM_SHIFT         17 /* must be same as eflags */
 #define HF_HALTED_SHIFT     18 /* CPU halted */
+#define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 
 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
@@ -158,6 +165,7 @@
 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 #define HF_HALTED_MASK       (1 << HF_HALTED_SHIFT)
+#define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 
 #define CR0_PE_MASK  (1 << 0)
 #define CR0_MP_MASK  (1 << 1)
@@ -258,6 +266,7 @@
 #define CPUID_MCA  (1 << 14)
 #define CPUID_CMOV (1 << 15)
 #define CPUID_PAT  (1 << 16)
+#define CPUID_PSE36   (1 << 17)
 #define CPUID_CLFLUSH (1 << 19)
 /* ... */
 #define CPUID_MMX  (1 << 23)
@@ -265,7 +274,7 @@
 #define CPUID_SSE  (1 << 25)
 #define CPUID_SSE2 (1 << 26)
 
-#define CPUID_EXT_SS3      (1 << 0)
+#define CPUID_EXT_SSE3     (1 << 0)
 #define CPUID_EXT_MONITOR  (1 << 3)
 #define CPUID_EXT_CX16     (1 << 13)
 
@@ -467,7 +476,7 @@ typedef struct CPUX86State {
        int i32;
         int64_t i64;
     } fp_convert;
-    
+   
     float_status sse_status;
     uint32_t mxcsr;
     XMMReg xmm_regs[CPU_NB_REGS];
@@ -495,7 +504,7 @@ typedef struct CPUX86State {
     uint32_t saved_esp;
     int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
 #endif
-    
+   
     /* exception/interrupt handling */
     jmp_buf jmp_env;
     int exception_index;
@@ -503,8 +512,10 @@ typedef struct CPUX86State {
     int exception_is_int;
     target_ulong exception_next_eip;
     target_ulong dr[8]; /* debug registers */
-    int interrupt_request; 
+    uint32_t smbase;
+    int interrupt_request;
     int user_mode_only; /* user mode only simulation */
+    int old_exception;  /* exception in flight */
 
     CPU_COMMON
 
@@ -519,9 +530,11 @@ typedef struct CPUX86State {
     uint32_t cpuid_xlevel;
     uint32_t cpuid_model[12];
     uint32_t cpuid_ext2_features;
-    
+    uint32_t cpuid_apic_id;
+   
 #ifdef USE_KQEMU
     int kqemu_enabled;
+    int last_io_time;
 #endif
     /* in order to simplify APIC support, we leave this pointer to the
        user */
@@ -537,14 +550,15 @@ void cpu_set_ferr(CPUX86State *s);
 
 /* this function must always be used to load data in the segment
    cache: it synchronizes the hflags with the segment cache values */
-static inline void cpu_x86_load_seg_cache(CPUX86State *env, 
+static inline void cpu_x86_load_seg_cache(CPUX86State *env,
                                           int seg_reg, unsigned int selector,
-                                          uint32_t base, unsigned int limit, 
+                                          target_ulong base,
+                                          unsigned int limit,
                                           unsigned int flags)
 {
     SegmentCache *sc;
     unsigned int new_hflags;
-    
+   
     sc = &env->segs[seg_reg];
     sc->selector = selector;
     sc->base = base;
@@ -559,7 +573,7 @@ static inline void cpu_x86_load_seg_cache(CPUX86State *env,
                 /* long mode */
                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
                 env->hflags &= ~(HF_ADDSEG_MASK);
-            } else 
+            } else
 #endif
             {
                 /* legacy / compatibility case */
@@ -573,7 +587,7 @@ static inline void cpu_x86_load_seg_cache(CPUX86State *env,
             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
         if (env->hflags & HF_CS64_MASK) {
             /* zero base assumed for DS, ES and SS in long mode */
-        } else if (!(env->cr[0] & CR0_PE_MASK) || 
+        } else if (!(env->cr[0] & CR0_PE_MASK) ||
                    (env->eflags & VM_MASK) ||
                    !(env->hflags & HF_CS32_MASK)) {
             /* XXX: try to avoid this test. The problem comes from the
@@ -583,12 +597,12 @@ static inline void cpu_x86_load_seg_cache(CPUX86State *env,
                translate-i386.c. */
             new_hflags |= HF_ADDSEG_MASK;
         } else {
-            new_hflags |= ((env->segs[R_DS].base | 
+            new_hflags |= ((env->segs[R_DS].base |
                             env->segs[R_ES].base |
-                            env->segs[R_SS].base) != 0) << 
+                            env->segs[R_SS].base) != 0) <<
                 HF_ADDSEG_SHIFT;
         }
-        env->hflags = (env->hflags & 
+        env->hflags = (env->hflags &
                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
     }
 }
@@ -616,8 +630,7 @@ void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
 /* you can call this signal handler from your SIGBUS and SIGSEGV
    signal handlers to inform the virtual CPU of exceptions. non zero
    is returned if the signal was handled by the virtual CPU.  */
-struct siginfo;
-int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
+int cpu_x86_signal_handler(int host_signum, void *pinfo,
                            void *puc);
 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 
@@ -629,6 +642,7 @@ void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
 #ifndef NO_CPU_IO_DEFS
 uint8_t cpu_get_apic_tpr(CPUX86State *env);
 #endif
+void cpu_smm_update(CPUX86State *env);
 
 /* will be suppressed */
 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
@@ -637,7 +651,23 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 
+#ifdef USE_KQEMU
+static inline int cpu_get_time_fast(void)
+{
+    int low, high;
+    asm volatile("rdtsc" : "=a" (low), "=d" (high));
+    return low;
+}
+#endif
+
 #define TARGET_PAGE_BITS 12
+
+#define CPUState CPUX86State
+#define cpu_init cpu_x86_init
+#define cpu_exec cpu_x86_exec
+#define cpu_gen_code cpu_x86_gen_code
+#define cpu_signal_handler cpu_x86_signal_handler
+
 #include "cpu-all.h"
 
 #endif /* CPU_I386_H */