int override; /* -1 if no override */
int prefix;
TCGMemOp aflag;
- int dflag;
+ TCGMemOp dflag;
target_ulong pc; /* pc = eip + cs_base */
int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
static state change (stop translation) */
return true;
}
+/* Select the size of a push/pop operation. */
+static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)
+{
+ if (CODE64(s)) {
+ return ot == MO_16 ? MO_16 : MO_64;
+ } else {
+ return ot;
+ }
+}
+
+/* Select only size 64 else 32. Used for SSE operand sizes. */
+static inline TCGMemOp mo_64_32(TCGMemOp ot)
+{
+#ifdef TARGET_X86_64
+ return ot == MO_64 ? MO_64 : MO_32;
+#else
+ return MO_32;
+#endif
+}
+
+/* Select size 8 if lsb of B is clear, else OT. Used for decoding
+ byte vs word opcodes. */
+static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)
+{
+ return b & 1 ? ot : MO_8;
+}
+
+/* Select size 8 if lsb of B is clear, else OT capped at 32.
+ Used for decoding operand size of port opcodes. */
+static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)
+{
+ return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8;
+}
+
static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
{
switch(ot) {
}
}
-static inline void gen_op_mov_reg_T0(TCGMemOp ot, int reg)
-{
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
-}
-
-static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg)
-{
- gen_op_mov_reg_v(ot, reg, cpu_T[1]);
-}
-
-static inline void gen_op_mov_reg_A0(TCGMemOp size, int reg)
-{
- gen_op_mov_reg_v(size, reg, cpu_A0);
-}
-
static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
{
if (ot == MO_8 && byte_reg_is_xH(reg)) {
}
}
-static inline void gen_op_mov_TN_reg(TCGMemOp ot, int t_index, int reg)
-{
- gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
-}
-
static inline void gen_op_movl_A0_reg(int reg)
{
tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
gen_op_addl_A0_im(val);
}
-static inline void gen_op_addl_T0_T1(void)
+static inline void gen_op_jmp_v(TCGv dest)
{
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
-}
-
-static inline void gen_op_jmp_T0(void)
-{
- tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
+ tcg_gen_st_tl(dest, cpu_env, offsetof(CPUX86State, eip));
}
static inline void gen_op_add_reg_im(TCGMemOp size, int reg, int32_t val)
if (d == OR_TMP0) {
gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(idx, d);
+ gen_op_mov_reg_v(idx, d, cpu_T[0]);
}
}
static inline void gen_jmp_im(target_ulong pc)
{
tcg_gen_movi_tl(cpu_tmp0, pc);
- tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
+ gen_op_jmp_v(cpu_tmp0);
}
static inline void gen_string_movl_A0_ESI(DisasContext *s)
return;
}
if (s->cc_op == CC_OP_CLR) {
- tcg_gen_movi_tl(cpu_cc_src, CC_Z);
+ tcg_gen_movi_tl(cpu_cc_src, CC_Z | CC_P);
set_cc_op(s, CC_OP_EFLAGS);
return;
}
static inline void gen_stos(DisasContext *s, TCGMemOp ot)
{
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
}
static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
{
if (d != OR_TMP0) {
- gen_op_mov_TN_reg(ot, 0, d);
+ gen_op_mov_v_reg(ot, cpu_T[0], d);
} else {
gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
}
set_cc_op(s1, CC_OP_SBBB + ot);
break;
case OP_ADDL:
- gen_op_addl_T0_T1();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_st_rm_T0_A0(s1, ot, d);
gen_op_update2_cc();
set_cc_op(s1, CC_OP_ADDB + ot);
static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
{
if (d != OR_TMP0) {
- gen_op_mov_TN_reg(ot, 0, d);
+ gen_op_mov_v_reg(ot, cpu_T[0], d);
} else {
gen_op_ld_v(s1, ot, cpu_T[0], cpu_A0);
}
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
if (op1 == OR_TMP0)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
op2 &= mask;
if (op2 != 0) {
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
op2 &= mask;
if (op1 == OR_TMP0)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
else
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
if (is_right) {
switch (ot) {
if (op1 == OR_TMP0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, op1);
+ gen_op_mov_v_reg(ot, cpu_T[0], op1);
}
count = tcg_temp_new();
static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)
{
if (s != OR_TMP1)
- gen_op_mov_TN_reg(ot, 1, s);
+ gen_op_mov_v_reg(ot, cpu_T[1], s);
switch(op) {
case OP_ROL:
gen_rot_rm_T1(s1, ot, d, 0);
break;
default:
case 2:
- disp = cpu_lduw_code(env, s->pc);
+ disp = (int16_t)cpu_lduw_code(env, s->pc);
s->pc += 2;
break;
}
- switch(rm) {
+
+ sum = cpu_A0;
+ switch (rm) {
case 0:
- gen_op_movl_A0_reg(R_EBX);
- gen_op_addl_A0_reg_sN(0, R_ESI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_ESI]);
break;
case 1:
- gen_op_movl_A0_reg(R_EBX);
- gen_op_addl_A0_reg_sN(0, R_EDI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_EDI]);
break;
case 2:
- gen_op_movl_A0_reg(R_EBP);
- gen_op_addl_A0_reg_sN(0, R_ESI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_ESI]);
break;
case 3:
- gen_op_movl_A0_reg(R_EBP);
- gen_op_addl_A0_reg_sN(0, R_EDI);
+ tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_EDI]);
break;
case 4:
- gen_op_movl_A0_reg(R_ESI);
+ sum = cpu_regs[R_ESI];
break;
case 5:
- gen_op_movl_A0_reg(R_EDI);
+ sum = cpu_regs[R_EDI];
break;
case 6:
- gen_op_movl_A0_reg(R_EBP);
+ sum = cpu_regs[R_EBP];
break;
default:
case 7:
- gen_op_movl_A0_reg(R_EBX);
+ sum = cpu_regs[R_EBX];
break;
}
- if (disp != 0)
- gen_op_addl_A0_im(disp);
+ tcg_gen_addi_tl(cpu_A0, sum, disp);
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
no_rm:
if (must_add_seg) {
if (override < 0) {
- if (rm == 2 || rm == 3 || rm == 6)
+ if (rm == 2 || rm == 3 || rm == 6) {
override = R_SS;
- else
+ } else {
override = R_DS;
+ }
}
gen_op_addl_A0_seg(s, override);
}
if (mod == 3) {
if (is_store) {
if (reg != OR_TMP0)
- gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
if (reg != OR_TMP0)
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
} else {
gen_lea_modrm(env, s, modrm);
if (is_store) {
if (reg != OR_TMP0)
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
if (reg != OR_TMP0)
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
}
}
tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2,
cpu_T[0], cpu_regs[reg]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
if (cc.mask != -1) {
tcg_temp_free(cc.reg);
}
}
-/* generate a push. It depends on ss32, addseg and dflag */
-static void gen_push_T0(DisasContext *s)
+/* Generate a push. It depends on ss32, addseg and dflag. */
+static void gen_push_v(DisasContext *s, TCGv val)
{
-#ifdef TARGET_X86_64
- if (CODE64(s)) {
- gen_op_movq_A0_reg(R_ESP);
- if (s->dflag) {
- gen_op_addq_A0_im(-8);
- gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0);
- } else {
- gen_op_addq_A0_im(-2);
- gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
- }
- gen_op_mov_reg_A0(MO_64, R_ESP);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- if (!s->dflag)
- gen_op_addl_A0_im(-2);
- else
- gen_op_addl_A0_im(-4);
- if (s->ss32) {
- if (s->addseg) {
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- }
- } else {
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- }
- gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
- if (s->ss32 && !s->addseg)
- gen_op_mov_reg_A0(MO_32, R_ESP);
- else
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
- }
-}
+ TCGMemOp a_ot, d_ot = mo_pushpop(s, s->dflag);
+ int size = 1 << d_ot;
+ TCGv new_esp = cpu_A0;
+
+ tcg_gen_subi_tl(cpu_A0, cpu_regs[R_ESP], size);
-/* generate a push. It depends on ss32, addseg and dflag */
-/* slower version for T1, only used for call Ev */
-static void gen_push_T1(DisasContext *s)
-{
-#ifdef TARGET_X86_64
if (CODE64(s)) {
- gen_op_movq_A0_reg(R_ESP);
- if (s->dflag) {
- gen_op_addq_A0_im(-8);
- gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0);
- } else {
- gen_op_addq_A0_im(-2);
- gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0);
- }
- gen_op_mov_reg_A0(MO_64, R_ESP);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- if (!s->dflag)
- gen_op_addl_A0_im(-2);
- else
- gen_op_addl_A0_im(-4);
- if (s->ss32) {
- if (s->addseg) {
- gen_op_addl_A0_seg(s, R_SS);
- }
- } else {
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
+ a_ot = MO_64;
+ } else if (s->ss32) {
+ a_ot = MO_32;
+ if (s->addseg) {
+ new_esp = cpu_tmp4;
+ tcg_gen_mov_tl(new_esp, cpu_A0);
gen_op_addl_A0_seg(s, R_SS);
+ } else {
+ tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
- gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0);
-
- if (s->ss32 && !s->addseg)
- gen_op_mov_reg_A0(MO_32, R_ESP);
- else
- gen_stack_update(s, (-2) << s->dflag);
+ } else {
+ a_ot = MO_16;
+ new_esp = cpu_tmp4;
+ tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
+ tcg_gen_mov_tl(new_esp, cpu_A0);
+ gen_op_addl_A0_seg(s, R_SS);
}
+
+ gen_op_st_v(s, d_ot, val, cpu_A0);
+ gen_op_mov_reg_v(a_ot, R_ESP, new_esp);
}
/* two step pop is necessary for precise exceptions */
-static void gen_pop_T0(DisasContext *s)
+static TCGMemOp gen_pop_T0(DisasContext *s)
{
-#ifdef TARGET_X86_64
+ TCGMemOp d_ot = mo_pushpop(s, s->dflag);
+ TCGv addr = cpu_A0;
+
if (CODE64(s)) {
- gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_v(s, s->dflag ? MO_64 : MO_16, cpu_T[0], cpu_A0);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- if (s->ss32) {
- if (s->addseg)
- gen_op_addl_A0_seg(s, R_SS);
- } else {
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- }
- gen_op_ld_v(s, s->dflag + 1, cpu_T[0], cpu_A0);
+ addr = cpu_regs[R_ESP];
+ } else if (!s->ss32) {
+ tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESP]);
+ gen_op_addl_A0_seg(s, R_SS);
+ } else if (s->addseg) {
+ tcg_gen_mov_tl(cpu_A0, cpu_regs[R_ESP]);
+ gen_op_addl_A0_seg(s, R_SS);
+ } else {
+ tcg_gen_ext32u_tl(cpu_A0, cpu_regs[R_ESP]);
}
+
+ gen_op_ld_v(s, d_ot, cpu_T[0], addr);
+ return d_ot;
}
-static void gen_pop_update(DisasContext *s)
+static void gen_pop_update(DisasContext *s, TCGMemOp ot)
{
-#ifdef TARGET_X86_64
- if (CODE64(s) && s->dflag) {
- gen_stack_update(s, 8);
- } else
-#endif
- {
- gen_stack_update(s, 2 << s->dflag);
- }
+ gen_stack_update(s, 1 << ot);
}
static void gen_stack_A0(DisasContext *s)
{
int i;
gen_op_movl_A0_reg(R_ESP);
- gen_op_addl_A0_im(-16 << s->dflag);
+ gen_op_addl_A0_im(-8 << s->dflag);
if (!s->ss32)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
- gen_op_mov_TN_reg(MO_32, 0, 7 - i);
- gen_op_st_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
- gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], 7 - i);
+ gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0);
+ gen_op_addl_A0_im(1 << s->dflag);
}
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
+ gen_op_mov_reg_v(MO_16 + s->ss32, R_ESP, cpu_T[1]);
}
/* NOTE: wrap around in 16 bit not fully handled */
if (!s->ss32)
tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
- tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
+ tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 8 << s->dflag);
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(MO_16 + s->dflag, 7 - i);
+ gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
+ gen_op_mov_reg_v(s->dflag, 7 - i, cpu_T[0]);
}
- gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_addl_A0_im(1 << s->dflag);
}
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
+ gen_op_mov_reg_v(MO_16 + s->ss32, R_ESP, cpu_T[1]);
}
static void gen_enter(DisasContext *s, int esp_addend, int level)
{
- TCGMemOp ot;
- int opsize;
+ TCGMemOp ot = mo_pushpop(s, s->dflag);
+ int opsize = 1 << ot;
level &= 0x1f;
#ifdef TARGET_X86_64
if (CODE64(s)) {
- ot = s->dflag ? MO_64 : MO_16;
- opsize = 1 << ot;
-
gen_op_movl_A0_reg(R_ESP);
gen_op_addq_A0_im(-opsize);
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
/* push bp */
- gen_op_mov_TN_reg(MO_32, 0, R_EBP);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EBP);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (level) {
/* XXX: must save state */
tcg_const_i32((ot == MO_64)),
cpu_T[1]);
}
- gen_op_mov_reg_T1(ot, R_EBP);
+ gen_op_mov_reg_v(ot, R_EBP, cpu_T[1]);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
- gen_op_mov_reg_T1(MO_64, R_ESP);
+ gen_op_mov_reg_v(MO_64, R_ESP, cpu_T[1]);
} else
#endif
{
- ot = s->dflag + MO_16;
- opsize = 2 << s->dflag;
-
gen_op_movl_A0_reg(R_ESP);
gen_op_addl_A0_im(-opsize);
if (!s->ss32)
if (s->addseg)
gen_op_addl_A0_seg(s, R_SS);
/* push bp */
- gen_op_mov_TN_reg(MO_32, 0, R_EBP);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EBP);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (level) {
/* XXX: must save state */
gen_helper_enter_level(cpu_env, tcg_const_i32(level),
- tcg_const_i32(s->dflag),
+ tcg_const_i32(s->dflag - 1),
cpu_T[1]);
}
- gen_op_mov_reg_T1(ot, R_EBP);
+ gen_op_mov_reg_v(ot, R_EBP, cpu_T[1]);
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
- gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP);
+ gen_op_mov_reg_v(MO_16 + s->ss32, R_ESP, cpu_T[1]);
}
}
break;
case 0x6e: /* movd mm, ea */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
} else
break;
case 0x16e: /* movd xmm, ea */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
offsetof(CPUX86State,xmm_regs[reg]));
break;
case 0x7e: /* movd ea, mm */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,fpregs[reg].mmx));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
break;
case 0x17e: /* movd ea, xmm */
#ifdef TARGET_X86_64
- if (s->dflag == 2) {
+ if (s->dflag == MO_64) {
tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
break;
case 0x22a: /* cvtsi2ss */
case 0x32a: /* cvtsi2sd */
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
case 0x32c: /* cvttsd2si */
case 0x22d: /* cvtss2si */
case 0x32d: /* cvtsd2si */
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
if ((b >> 8) & 1) {
goto illegal_op;
#endif
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0xc4: /* pinsrw */
case 0x1c4:
case 0x1c5:
if (mod != 3)
goto illegal_op;
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
val = cpu_ldub_code(env, s->pc++);
if (b1) {
val &= 7;
offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
}
reg = ((modrm >> 3) & 7) | rex_r;
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x1d6: /* movq ea, xmm */
if (mod != 3) {
}
if ((b & 0xff) == 0xf0) {
ot = MO_8;
- } else if (s->dflag != 2) {
+ } else if (s->dflag != MO_64) {
ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
ot = MO_64;
gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
cpu_T[0], tcg_const_i32(8 << ot));
- ot = (s->dflag == 2) ? MO_64 : MO_32;
- gen_op_mov_reg_T0(ot, reg);
+ ot = mo_64_32(s->dflag);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x1f0: /* crc32 or movbe */
if (!(s->cpuid_ext_features & CPUID_EXT_MOVBE)) {
goto illegal_op;
}
- if (s->dflag != 2) {
+ if (s->dflag != MO_64) {
ot = (s->prefix & PREFIX_DATA ? MO_16 : MO_32);
} else {
ot = MO_64;
if ((b & 1) == 0) {
tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
s->mem_index, ot | MO_BE);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_regs[reg], cpu_A0,
s->mem_index, ot | MO_BE);
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
{
TCGv bound, zero;
tcg_gen_subi_tl(cpu_T[1], cpu_T[1], 1);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
}
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_ext8u_tl(cpu_T[1], cpu_regs[s->vex_v]);
{
tcg_gen_movi_tl(cpu_A0, -1);
tcg_gen_shl_tl(cpu_A0, cpu_A0, cpu_T[1]);
tcg_gen_andc_tl(cpu_T[0], cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (ot) {
default:
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
- if (s->dflag == 2) {
+ if (ot == MO_64) {
tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
} else {
tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Note that by zero-extending the mask operand, we
automatically handle zero-extending the result. */
- if (s->dflag == 2) {
+ if (ot == MO_64) {
tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
} else {
tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
TCGv carry_in, carry_out, zero;
int end_op;
- ot = (s->dflag == 2 ? MO_64 : MO_32);
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Re-use the carry-out from a previous round. */
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = (s->dflag == 2 ? MO_64 : MO_32);
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
if (ot == MO_64) {
tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63);
}
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x0f3:
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (reg & 7) {
case 1: /* blsr By,Ey */
tcg_gen_neg_tl(cpu_T[1], cpu_T[0]);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(ot, s->vex_v);
+ gen_op_mov_reg_v(ot, s->vex_v, cpu_T[0]);
gen_op_update2_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
goto illegal_op;
if (sse_fn_eppi == SSE_SPECIAL) {
- ot = (s->dflag == 2) ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
rm = (modrm & 7) | REX_B(s);
if (mod != 3)
gen_lea_modrm(env, s, modrm);
tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_UB);
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_W(val & 7)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_LEUW);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_LEUL);
break;
case 0x20: /* pinsrb */
if (mod == 3) {
- gen_op_mov_TN_reg(MO_32, 0, rm);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
} else {
tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_UB);
if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
set_cc_op(s, CC_OP_EFLAGS);
- if (s->dflag == 2)
+ if (s->dflag == MO_64) {
/* The helper must use entire 64-bit gp registers */
val |= 1 << 8;
+ }
}
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
|| s->vex_l != 0) {
goto illegal_op;
}
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
b = cpu_ldub_code(env, s->pc++);
if (ot == MO_64) {
tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, b & 31);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
default:
if (is_xmm) {
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
if (mod != 3) {
+ int sz = 4;
+
gen_lea_modrm(env, s, modrm);
op2_offset = offsetof(CPUX86State,xmm_t0);
- if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
- b == 0xc2)) {
- /* specific case for SSE single instructions */
+
+ switch (b) {
+ case 0x50 ... 0x5a:
+ case 0x5c ... 0x5f:
+ case 0xc2:
+ /* Most sse scalar operations. */
if (b1 == 2) {
- /* 32 bit access */
- gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
- tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
+ sz = 2;
+ } else if (b1 == 3) {
+ sz = 3;
+ }
+ break;
+
+ case 0x2e: /* ucomis[sd] */
+ case 0x2f: /* comis[sd] */
+ if (b1 == 0) {
+ sz = 2;
} else {
- /* 64 bit access */
- gen_ldq_env_A0(s, offsetof(CPUX86State,
- xmm_t0.XMM_D(0)));
+ sz = 3;
}
- } else {
+ break;
+ }
+
+ switch (sz) {
+ case 2:
+ /* 32 bit access */
+ gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
+ tcg_gen_st32_tl(cpu_T[0], cpu_env,
+ offsetof(CPUX86State,xmm_t0.XMM_L(0)));
+ break;
+ case 3:
+ /* 64 bit access */
+ gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_D(0)));
+ break;
+ default:
+ /* 128 bit access */
gen_ldo_env_A0(s, op2_offset);
+ break;
}
} else {
rm = (modrm & 7) | REX_B(s);
static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
target_ulong pc_start)
{
- int b, prefixes, dflag;
+ int b, prefixes;
int shift;
- TCGMemOp ot, aflag;
+ TCGMemOp ot, aflag, dflag;
int modrm, reg, rm, mod, op, opreg, val;
target_ulong next_eip, tval;
int rex_w, rex_r;
/* In 64-bit mode, the default data size is 32-bit. Select 64-bit
data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
over 0x66 if both are present. */
- dflag = (rex_w > 0 ? 2 : prefixes & PREFIX_DATA ? 0 : 1);
+ dflag = (rex_w > 0 ? MO_64 : prefixes & PREFIX_DATA ? MO_16 : MO_32);
/* In 64-bit mode, 0x67 selects 32-bit addressing. */
aflag = (prefixes & PREFIX_ADR ? MO_32 : MO_64);
} else {
/* In 16/32-bit mode, 0x66 selects the opposite data size. */
- dflag = s->code32;
- if (prefixes & PREFIX_DATA) {
- dflag ^= 1;
+ if (s->code32 ^ ((prefixes & PREFIX_DATA) != 0)) {
+ dflag = MO_32;
+ } else {
+ dflag = MO_16;
}
/* In 16/32-bit mode, 0x67 selects the opposite addressing. */
if (s->code32 ^ ((prefixes & PREFIX_ADR) != 0)) {
op = (b >> 3) & 7;
f = (b >> 1) & 3;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
switch(f) {
case 0: /* OP Ev, Gv */
/* xor reg, reg optimisation */
set_cc_op(s, CC_OP_CLR);
tcg_gen_movi_tl(cpu_T[0], 0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
} else {
opreg = rm;
}
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
gen_op(s, op, ot, opreg);
break;
case 1: /* OP Gv, Ev */
} else if (op == OP_XORL && rm == reg) {
goto xor_zero;
} else {
- gen_op_mov_TN_reg(ot, 1, rm);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
}
gen_op(s, op, ot, reg);
break;
{
int val;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
/**************************/
/* inc, dec, and other misc arith */
case 0x40 ... 0x47: /* inc Gv */
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), 1);
break;
case 0x48 ... 0x4f: /* dec Gv */
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
gen_inc(s, ot, OR_EAX + (b & 7), -1);
break;
case 0xf6: /* GRP3 */
case 0xf7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
switch(op) {
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
break;
case 3: /* neg */
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
gen_op_update_neg_cc();
set_cc_op(s, CC_OP_SUBB + ot);
case 4: /* mul */
switch(ot) {
case MO_8:
- gen_op_mov_TN_reg(MO_8, 1, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 1, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
set_cc_op(s, CC_OP_MULW);
break;
case 5: /* imul */
switch(ot) {
case MO_8:
- gen_op_mov_TN_reg(MO_8, 1, R_EAX);
+ gen_op_mov_v_reg(MO_8, cpu_T[1], R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
set_cc_op(s, CC_OP_MULB);
break;
case MO_16:
- gen_op_mov_TN_reg(MO_16, 1, R_EAX);
+ gen_op_mov_v_reg(MO_16, cpu_T[1], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
set_cc_op(s, CC_OP_MULW);
break;
default:
case 0xfe: /* GRP4 */
case 0xff: /* GRP5 */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
/* operand size for jumps is 64 bit */
ot = MO_64;
} else if (op == 3 || op == 5) {
- ot = dflag ? MO_32 + (rex_w == 1) : MO_16;
+ ot = dflag != MO_16 ? MO_32 + (rex_w == 1) : MO_16;
} else if (op == 6) {
/* default push size is 64 bit */
- ot = dflag ? MO_64 : MO_16;
+ ot = mo_pushpop(s, dflag);
}
}
if (mod != 3) {
if (op >= 2 && op != 3 && op != 5)
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
switch(op) {
break;
case 2: /* call Ev */
/* XXX: optimize if memory (no 'and' is necessary) */
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
next_eip = s->pc - s->cs_base;
tcg_gen_movi_tl(cpu_T[1], next_eip);
- gen_push_T1(s);
- gen_op_jmp_T0();
+ gen_push_v(s, cpu_T[1]);
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 3: /* lcall Ev */
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_lcall:
if (s->pe && !s->vm86) {
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
- tcg_const_i32(dflag),
+ tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - pc_start));
} else {
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1],
- tcg_const_i32(dflag),
+ tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - s->cs_base));
}
gen_eob(s);
break;
case 4: /* jmp Ev */
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
}
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 5: /* ljmp Ev */
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
do_ljmp:
if (s->pe && !s->vm86) {
tcg_const_i32(s->pc - pc_start));
} else {
gen_op_movl_seg_T0_vm(R_CS);
- tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[1]);
}
gen_eob(s);
break;
case 6: /* push Ev */
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
default:
goto illegal_op;
case 0x84: /* test Ev, Gv */
case 0x85:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
case 0xa8: /* test eAX, Iv */
case 0xa9:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
val = insn_get(env, s, ot);
- gen_op_mov_TN_reg(ot, 0, OR_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[0], OR_EAX);
tcg_gen_movi_tl(cpu_T[1], val);
gen_op_testl_T0_T1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
case 0x98: /* CWDE/CBW */
+ switch (dflag) {
#ifdef TARGET_X86_64
- if (dflag == 2) {
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ case MO_64:
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_64, R_EAX);
- } else
+ gen_op_mov_reg_v(MO_64, R_EAX, cpu_T[0]);
+ break;
#endif
- if (dflag == 1) {
- gen_op_mov_TN_reg(MO_16, 0, R_EAX);
+ case MO_32:
+ gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_32, R_EAX);
- } else {
- gen_op_mov_TN_reg(MO_8, 0, R_EAX);
+ gen_op_mov_reg_v(MO_32, R_EAX, cpu_T[0]);
+ break;
+ case MO_16:
+ gen_op_mov_v_reg(MO_8, cpu_T[0], R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
+ break;
+ default:
+ tcg_abort();
}
break;
case 0x99: /* CDQ/CWD */
+ switch (dflag) {
#ifdef TARGET_X86_64
- if (dflag == 2) {
- gen_op_mov_TN_reg(MO_64, 0, R_EAX);
+ case MO_64:
+ gen_op_mov_v_reg(MO_64, cpu_T[0], R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
- gen_op_mov_reg_T0(MO_64, R_EDX);
- } else
+ gen_op_mov_reg_v(MO_64, R_EDX, cpu_T[0]);
+ break;
#endif
- if (dflag == 1) {
- gen_op_mov_TN_reg(MO_32, 0, R_EAX);
+ case MO_32:
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
- gen_op_mov_reg_T0(MO_32, R_EDX);
- } else {
- gen_op_mov_TN_reg(MO_16, 0, R_EAX);
+ gen_op_mov_reg_v(MO_32, R_EDX, cpu_T[0]);
+ break;
+ case MO_16:
+ gen_op_mov_v_reg(MO_16, cpu_T[0], R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
+ break;
+ default:
+ tcg_abort();
}
break;
case 0x1af: /* imul Gv, Ev */
case 0x69: /* imul Gv, Ev, I */
case 0x6b:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
if (b == 0x69)
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[1], val);
} else {
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
}
switch (ot) {
#ifdef TARGET_X86_64
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
}
set_cc_op(s, CC_OP_MULB + ot);
break;
case 0x1c0:
case 0x1c1: /* xadd Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_TN_reg(ot, 1, rm);
- gen_op_addl_T0_T1();
- gen_op_mov_reg_T1(ot, reg);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_op_addl_T0_T1();
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
gen_op_update2_cc();
set_cc_op(s, CC_OP_ADDB + ot);
int label1, label2;
TCGv t0, t1, t2, a0;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
if ((mod == 3) || ((modrm & 0x38) != 0x8))
goto illegal_op;
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
goto illegal_op;
gen_jmp_im(pc_start - s->cs_base);
/**************************/
/* push/pop */
case 0x50 ... 0x57: /* push */
- gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s));
- gen_push_T0(s);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], (b & 7) | REX_B(s));
+ gen_push_v(s, cpu_T[0]);
break;
case 0x58 ... 0x5f: /* pop */
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
- gen_pop_update(s);
- gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
+ gen_pop_update(s, ot);
+ gen_op_mov_reg_v(ot, (b & 7) | REX_B(s), cpu_T[0]);
break;
case 0x60: /* pusha */
if (CODE64(s))
break;
case 0x68: /* push Iv */
case 0x6a:
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
+ ot = mo_pushpop(s, dflag);
if (b == 0x68)
val = insn_get(env, s, ot);
else
val = (int8_t)insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x8f: /* pop Ev */
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
- } else {
- ot = dflag + MO_16;
- }
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
if (mod == 3) {
/* NOTE: order is important for pop %sp */
- gen_pop_update(s);
+ gen_pop_update(s, ot);
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
/* NOTE: order is important too for MMU exceptions */
s->popl_esp_hack = 1 << ot;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
s->popl_esp_hack = 0;
- gen_pop_update(s);
+ gen_pop_update(s, ot);
}
break;
case 0xc8: /* enter */
case 0xc9: /* leave */
/* XXX: exception not precise (ESP is updated before potential exception) */
if (CODE64(s)) {
- gen_op_mov_TN_reg(MO_64, 0, R_EBP);
- gen_op_mov_reg_T0(MO_64, R_ESP);
+ gen_op_mov_v_reg(MO_64, cpu_T[0], R_EBP);
+ gen_op_mov_reg_v(MO_64, R_ESP, cpu_T[0]);
} else if (s->ss32) {
- gen_op_mov_TN_reg(MO_32, 0, R_EBP);
- gen_op_mov_reg_T0(MO_32, R_ESP);
- } else {
- gen_op_mov_TN_reg(MO_16, 0, R_EBP);
- gen_op_mov_reg_T0(MO_16, R_ESP);
- }
- gen_pop_T0(s);
- if (CODE64(s)) {
- ot = dflag ? MO_64 : MO_16;
+ gen_op_mov_v_reg(MO_32, cpu_T[0], R_EBP);
+ gen_op_mov_reg_v(MO_32, R_ESP, cpu_T[0]);
} else {
- ot = dflag + MO_16;
+ gen_op_mov_v_reg(MO_16, cpu_T[0], R_EBP);
+ gen_op_mov_reg_v(MO_16, R_ESP, cpu_T[0]);
}
- gen_op_mov_reg_T0(ot, R_EBP);
- gen_pop_update(s);
+ ot = gen_pop_T0(s);
+ gen_op_mov_reg_v(ot, R_EBP, cpu_T[0]);
+ gen_pop_update(s, ot);
break;
case 0x06: /* push es */
case 0x0e: /* push cs */
if (CODE64(s))
goto illegal_op;
gen_op_movl_T0_seg(b >> 3);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x1a0: /* push fs */
case 0x1a8: /* push gs */
gen_op_movl_T0_seg((b >> 3) & 7);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
break;
case 0x07: /* pop es */
case 0x17: /* pop ss */
if (CODE64(s))
goto illegal_op;
reg = b >> 3;
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
if (reg == R_SS) {
/* if reg == SS, inhibit interrupts/trace. */
/* If several instructions disable interrupts, only the
break;
case 0x1a1: /* pop fs */
case 0x1a9: /* pop gs */
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
if (s->is_jmp) {
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
/* mov */
case 0x88:
case 0x89: /* mov Gv, Ev */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
break;
case 0xc6:
case 0xc7: /* mov Ev, Iv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod != 3) {
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
+ gen_op_mov_reg_v(ot, (modrm & 7) | REX_B(s), cpu_T[0]);
}
break;
case 0x8a:
case 0x8b: /* mov Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = MO_16 + dflag;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x8e: /* mov seg, Gv */
modrm = cpu_ldub_code(env, s->pc++);
if (reg >= 6)
goto illegal_op;
gen_op_movl_T0_seg(reg);
- if (mod == 3)
- ot = MO_16 + dflag;
- else
- ot = MO_16;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
TCGMemOp s_ot;
/* d_ot is the size of destination */
- d_ot = dflag + MO_16;
+ d_ot = dflag;
/* ot is the size of source */
ot = (b & 1) + MO_8;
/* s_ot is the sign+size of source */
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
switch (s_ot) {
case MO_UB:
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
break;
}
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
}
}
break;
case 0x8d: /* lea */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
s->addseg = 0;
gen_lea_modrm(env, s, modrm);
s->addseg = val;
- gen_op_mov_reg_A0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_A0);
break;
case 0xa0: /* mov EAX, Ov */
{
target_ulong offset_addr;
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
switch (s->aflag) {
#ifdef TARGET_X86_64
case MO_64:
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
} else {
- gen_op_mov_TN_reg(ot, 0, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[0], R_EAX);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
}
}
gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(MO_8, R_EAX);
+ gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
val = insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s));
+ gen_op_mov_reg_v(MO_8, (b & 7) | REX_B(s), cpu_T[0]);
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
- if (dflag == 2) {
+ if (dflag == MO_64) {
uint64_t tmp;
/* 64 bit case */
tmp = cpu_ldq_code(env, s->pc);
s->pc += 8;
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], tmp);
- gen_op_mov_reg_T0(MO_64, reg);
+ gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
break;
case 0x91 ... 0x97: /* xchg R, EAX */
do_xchg_reg_eax:
- ot = dflag + MO_16;
+ ot = dflag;
reg = (b & 7) | REX_B(s);
rm = R_EAX;
goto do_xchg_reg;
case 0x86:
case 0x87: /* xchg Ev, Gv */
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
if (mod == 3) {
rm = (modrm & 7) | REX_B(s);
do_xchg_reg:
- gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_TN_reg(ot, 1, rm);
- gen_op_mov_reg_T0(ot, rm);
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
} else {
gen_lea_modrm(env, s, modrm);
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
/* for xchg, lock is implicit */
if (!(prefixes & PREFIX_LOCK))
gen_helper_lock();
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
if (!(prefixes & PREFIX_LOCK))
gen_helper_unlock();
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
break;
case 0xc4: /* les Gv */
case 0x1b5: /* lgs Gv */
op = R_GS;
do_lxx:
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
goto illegal_op;
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[1], cpu_A0);
- gen_add_A0_im(s, 1 << (ot - MO_16 + 1));
+ gen_add_A0_im(s, 1 << ot);
/* load the segment first to handle exceptions properly */
gen_op_ld_v(s, MO_16, cpu_T[0], cpu_A0);
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
- gen_op_mov_reg_T1(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[1]);
if (s->is_jmp) {
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
shift = 2;
grp2:
{
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
op = (modrm >> 3) & 7;
op = 1;
shift = 0;
do_shiftd:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
} else {
opreg = rm;
}
- gen_op_mov_TN_reg(ot, 1, reg);
+ gen_op_mov_v_reg(ot, cpu_T[1], reg);
if (shift) {
TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++));
case 0x0c: /* fldenv mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x0d: /* fldcw mem */
tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
case 0x0e: /* fnstenv mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
case 0x2c: /* frstor mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x2e: /* fnsave mem */
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
+ gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(dflag - 1));
break;
case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
case 0:
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
break;
default:
goto illegal_op;
case 0xa4: /* movsS */
case 0xa5:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
case 0xaa: /* stosS */
case 0xab:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
-
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
break;
case 0xac: /* lodsS */
case 0xad:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
} else {
break;
case 0xae: /* scasS */
case 0xaf:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
case 0xa6: /* cmpsS */
case 0xa7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag + MO_16;
+ ot = mo_b_d(b, dflag);
if (prefixes & PREFIX_REPNZ) {
gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
} else if (prefixes & PREFIX_REPZ) {
break;
case 0x6c: /* insS */
case 0x6d:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
break;
case 0x6e: /* outsS */
case 0x6f:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes) | 4);
case 0xe4:
case 0xe5:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
val = cpu_ldub_code(env, s->pc++);
+ tcg_gen_movi_tl(cpu_T[0], val);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
if (use_icount)
gen_io_start();
tcg_gen_movi_i32(cpu_tmp2_i32, val);
gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
- gen_op_mov_reg_T1(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
if (use_icount) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
break;
case 0xe6:
case 0xe7:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
val = cpu_ldub_code(env, s->pc++);
+ tcg_gen_movi_tl(cpu_T[0], val);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
- gen_op_mov_TN_reg(ot, 1, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
if (use_icount)
gen_io_start();
break;
case 0xec:
case 0xed:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
gen_io_start();
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
- gen_op_mov_reg_T1(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
if (use_icount) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
break;
case 0xee:
case 0xef:
- if ((b & 1) == 0)
- ot = MO_8;
- else
- ot = dflag ? MO_32 : MO_16;
+ ot = mo_b_d32(b, dflag);
tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]);
gen_check_io(s, ot, pc_start - s->cs_base,
svm_is_rep(prefixes));
- gen_op_mov_TN_reg(ot, 1, R_EAX);
+ gen_op_mov_v_reg(ot, cpu_T[1], R_EAX);
if (use_icount)
gen_io_start();
case 0xc2: /* ret im */
val = cpu_ldsw_code(env, s->pc);
s->pc += 2;
- gen_pop_T0(s);
- if (CODE64(s) && s->dflag)
- s->dflag = 2;
- gen_stack_update(s, val + (2 << s->dflag));
- if (s->dflag == 0) {
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
- }
- gen_op_jmp_T0();
+ ot = gen_pop_T0(s);
+ gen_stack_update(s, val + (1 << ot));
+ /* Note that gen_pop_T0 uses a zero-extending load. */
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 0xc3: /* ret */
- gen_pop_T0(s);
- gen_pop_update(s);
- if (s->dflag == 0) {
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
- }
- gen_op_jmp_T0();
+ ot = gen_pop_T0(s);
+ gen_pop_update(s, ot);
+ /* Note that gen_pop_T0 uses a zero-extending load. */
+ gen_op_jmp_v(cpu_T[0]);
gen_eob(s);
break;
case 0xca: /* lret im */
if (s->pe && !s->vm86) {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag),
+ gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1),
tcg_const_i32(val));
} else {
gen_stack_A0(s);
/* pop offset */
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
+ gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
/* NOTE: keeping EIP updated is not a problem in case of
exception */
- gen_op_jmp_T0();
+ gen_op_jmp_v(cpu_T[0]);
/* pop selector */
- gen_op_addl_A0_im(2 << s->dflag);
- gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0);
+ gen_op_addl_A0_im(1 << dflag);
+ gen_op_ld_v(s, dflag, cpu_T[0], cpu_A0);
gen_op_movl_seg_T0_vm(R_CS);
/* add stack offset */
- gen_stack_update(s, val + (4 << s->dflag));
+ gen_stack_update(s, val + (2 << dflag));
}
gen_eob(s);
break;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
if (!s->pe) {
/* real mode */
- gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
set_cc_op(s, CC_OP_EFLAGS);
} else if (s->vm86) {
if (s->iopl != 3) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
set_cc_op(s, CC_OP_EFLAGS);
}
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag),
+ gen_helper_iret_protected(cpu_env, tcg_const_i32(dflag - 1),
tcg_const_i32(s->pc - s->cs_base));
set_cc_op(s, CC_OP_EFLAGS);
}
break;
case 0xe8: /* call im */
{
- if (dflag)
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
- else
+ } else {
tval = (int16_t)insn_get(env, s, MO_16);
+ }
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
- else if(!CODE64(s))
+ } else if (!CODE64(s)) {
tval &= 0xffffffff;
+ }
tcg_gen_movi_tl(cpu_T[0], next_eip);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
gen_jmp(s, tval);
}
break;
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
}
goto do_lcall;
case 0xe9: /* jmp im */
- if (dflag)
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
- else
+ } else {
tval = (int16_t)insn_get(env, s, MO_16);
+ }
tval += s->pc - s->cs_base;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
- else if(!CODE64(s))
+ } else if (!CODE64(s)) {
tval &= 0xffffffff;
+ }
gen_jmp(s, tval);
break;
case 0xea: /* ljmp im */
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
offset = insn_get(env, s, ot);
selector = insn_get(env, s, MO_16);
case 0xeb: /* jmp Jb */
tval = (int8_t)insn_get(env, s, MO_8);
tval += s->pc - s->cs_base;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
+ }
gen_jmp(s, tval);
break;
case 0x70 ... 0x7f: /* jcc Jb */
tval = (int8_t)insn_get(env, s, MO_8);
goto do_jcc;
case 0x180 ... 0x18f: /* jcc Jv */
- if (dflag) {
+ if (dflag != MO_16) {
tval = (int32_t)insn_get(env, s, MO_32);
} else {
tval = (int16_t)insn_get(env, s, MO_16);
do_jcc:
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
+ }
gen_jcc(s, b, tval, next_eip);
break;
if (!(s->cpuid_features & CPUID_CMOV)) {
goto illegal_op;
}
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_cmovcc1(env, s, ot, b, modrm, reg);
} else {
gen_update_cc_op(s);
gen_helper_read_eflags(cpu_T[0], cpu_env);
- gen_push_T0(s);
+ gen_push_v(s, cpu_T[0]);
}
break;
case 0x9d: /* popf */
if (s->vm86 && s->iopl != 3) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
if (s->cpl == 0) {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK |
}
} else {
if (s->cpl <= s->iopl) {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK |
AC_MASK |
& 0xffff));
}
} else {
- if (s->dflag) {
+ if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK)));
}
}
}
- gen_pop_update(s);
+ gen_pop_update(s, ot);
set_cc_op(s, CC_OP_EFLAGS);
/* abort translation because TF/AC flag may change */
gen_jmp_im(s->pc - s->cs_base);
case 0x9e: /* sahf */
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
- gen_op_mov_TN_reg(MO_8, 0, R_AH);
+ gen_op_mov_v_reg(MO_8, cpu_T[0], R_AH);
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
gen_compute_eflags(s);
/* Note: gen_compute_eflags() only gives the condition codes */
tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02);
- gen_op_mov_reg_T0(MO_8, R_AH);
+ gen_op_mov_reg_v(MO_8, R_AH, cpu_T[0]);
break;
case 0xf5: /* cmc */
gen_compute_eflags(s);
/************************/
/* bit operations */
case 0x1ba: /* bt/bts/btr/btc Gv, im */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
op = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
/* load shift */
val = cpu_ldub_code(env, s->pc++);
case 0x1bb: /* btc */
op = 3;
do_btx:
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
mod = (modrm >> 6) & 3;
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_TN_reg(MO_32, 1, reg);
+ gen_op_mov_v_reg(MO_32, cpu_T[1], reg);
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
/* specific case: we need to add a displacement */
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
}
bt_op:
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
tcg_gen_movi_tl(cpu_cc_dst, 0);
break;
case 0x1bc: /* bsf / tzcnt */
case 0x1bd: /* bsr / lzcnt */
- ot = dflag + MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[0], cpu_cc_dst, cpu_tmp0,
cpu_regs[reg], cpu_T[0]);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
/************************/
/* bcd */
case 0x62: /* bound */
if (CODE64(s))
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = (modrm >> 3) & 7;
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
- gen_op_mov_TN_reg(ot, 0, reg);
+ gen_op_mov_v_reg(ot, cpu_T[0], reg);
gen_lea_modrm(env, s, modrm);
gen_jmp_im(pc_start - s->cs_base);
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
case 0x1c8 ... 0x1cf: /* bswap reg */
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
- if (dflag == 2) {
- gen_op_mov_TN_reg(MO_64, 0, reg);
+ if (dflag == MO_64) {
+ gen_op_mov_v_reg(MO_64, cpu_T[0], reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_64, reg);
+ gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
- gen_op_mov_TN_reg(MO_32, 0, reg);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], reg);
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_32, reg);
+ gen_op_mov_reg_v(MO_32, reg, cpu_T[0]);
}
break;
case 0xd6: /* salc */
goto illegal_op;
gen_compute_eflags_c(s, cpu_T[0]);
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_8, R_EAX);
+ gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
break;
case 0xe0: /* loopnz */
case 0xe1: /* loopz */
tval = (int8_t)insn_get(env, s, MO_8);
next_eip = s->pc - s->cs_base;
tval += next_eip;
- if (s->dflag == 0)
+ if (dflag == MO_16) {
tval &= 0xffff;
+ }
l1 = gen_new_label();
l2 = gen_new_label();
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_sysexit(cpu_env, tcg_const_i32(dflag));
+ gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1));
gen_eob(s);
}
break;
} else {
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag));
+ gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1));
/* condition codes are modified only in long mode */
if (s->lma) {
set_cc_op(s, CC_OP_EFLAGS);
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
- ot = MO_16;
- if (mod == 3)
- ot += s->dflag;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 2: /* lldt */
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
- ot = MO_16;
- if (mod == 3)
- ot += s->dflag;
+ ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 3: /* ltr */
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0);
gen_add_A0_im(s, 2);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
gen_op_ld_v(s, MO_16, cpu_T[1], cpu_A0);
gen_add_A0_im(s, 2);
gen_op_ld_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0);
- if (s->dflag == 0) {
+ if (dflag == MO_16) {
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffff);
}
if (op == 2) {
if (CODE64(s)) {
int d_ot;
/* d_ot is the size of destination */
- d_ot = dflag + MO_16;
+ d_ot = dflag;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
- gen_op_mov_TN_reg(MO_32, 0, rm);
+ gen_op_mov_v_reg(MO_32, cpu_T[0], rm);
/* sign extend */
if (d_ot == MO_64) {
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
}
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
}
} else
#endif
TCGv t0;
if (!s->pe || s->vm86)
goto illegal_op;
- ot = dflag ? MO_32 : MO_16;
+ ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
if (b & 2) {
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {
gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg));
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
break;
default:
goto illegal_op;
if (b & 2) {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
- gen_op_mov_TN_reg(ot, 0, rm);
+ gen_op_mov_v_reg(ot, cpu_T[0], rm);
gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
}
break;
case 0x1c3: /* MOVNTI reg, mem */
if (!(s->cpuid_features & CPUID_SSE2))
goto illegal_op;
- ot = s->dflag == 2 ? MO_64 : MO_32;
+ ot = mo_64_32(dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
if (mod == 3)
gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2)));
+ gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64));
break;
case 1: /* fxrstor */
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
gen_lea_modrm(env, s, modrm);
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
- gen_helper_fxrstor(cpu_env, cpu_A0,
- tcg_const_i32((s->dflag == 2)));
+ gen_helper_fxrstor(cpu_env, cpu_A0, tcg_const_i32(dflag == MO_64));
break;
case 2: /* ldmxcsr */
case 3: /* stmxcsr */
modrm = cpu_ldub_code(env, s->pc++);
reg = ((modrm >> 3) & 7) | rex_r;
- if (s->prefix & PREFIX_DATA)
+ if (s->prefix & PREFIX_DATA) {
ot = MO_16;
- else if (s->dflag != 2)
- ot = MO_32;
- else
- ot = MO_64;
+ } else {
+ ot = mo_64_32(dflag);
+ }
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
set_cc_op(s, CC_OP_EFLAGS);
break;
void optimize_flags_init(void)
{
+ static const char reg_names[CPU_NB_REGS][4] = {
+#ifdef TARGET_X86_64
+ [R_EAX] = "rax",
+ [R_EBX] = "rbx",
+ [R_ECX] = "rcx",
+ [R_EDX] = "rdx",
+ [R_ESI] = "rsi",
+ [R_EDI] = "rdi",
+ [R_EBP] = "rbp",
+ [R_ESP] = "rsp",
+ [8] = "r8",
+ [9] = "r9",
+ [10] = "r10",
+ [11] = "r11",
+ [12] = "r12",
+ [13] = "r13",
+ [14] = "r14",
+ [15] = "r15",
+#else
+ [R_EAX] = "eax",
+ [R_EBX] = "ebx",
+ [R_ECX] = "ecx",
+ [R_EDX] = "edx",
+ [R_ESI] = "esi",
+ [R_EDI] = "edi",
+ [R_EBP] = "ebp",
+ [R_ESP] = "esp",
+#endif
+ };
+ int i;
+
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State, cc_op), "cc_op");
cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src2),
"cc_src2");
-#ifdef TARGET_X86_64
- cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EAX]), "rax");
- cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ECX]), "rcx");
- cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDX]), "rdx");
- cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBX]), "rbx");
- cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESP]), "rsp");
- cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBP]), "rbp");
- cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESI]), "rsi");
- cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDI]), "rdi");
- cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[8]), "r8");
- cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[9]), "r9");
- cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[10]), "r10");
- cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[11]), "r11");
- cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[12]), "r12");
- cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[13]), "r13");
- cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[14]), "r14");
- cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUX86State, regs[15]), "r15");
-#else
- cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EAX]), "eax");
- cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ECX]), "ecx");
- cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDX]), "edx");
- cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBX]), "ebx");
- cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESP]), "esp");
- cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EBP]), "ebp");
- cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_ESI]), "esi");
- cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUX86State, regs[R_EDI]), "edi");
-#endif
+ for (i = 0; i < CPU_NB_REGS; ++i) {
+ cpu_regs[i] = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUX86State, regs[i]),
+ reg_names[i]);
+ }
}
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
gen_tb_start();
for(;;) {
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == pc_ptr &&
!((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
gen_debug(dc, pc_ptr - dc->cs_base);
projects / mirror_qemu.git / blobdiff