#if !defined (__MIPS_CPU_H__)
#define __MIPS_CPU_H__
+#define TARGET_HAS_ICE 1
+
+#include "config.h"
#include "mips-defs.h"
#include "cpu-defs.h"
-#include "config.h"
#include "softfloat.h"
+// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
+// XXX: move that elsewhere
+#if defined(HOST_SOLARIS) && SOLARISREV < 10
+typedef unsigned char uint_fast8_t;
+typedef unsigned int uint_fast16_t;
+#endif
+
typedef union fpr_t fpr_t;
union fpr_t {
- double d;
- float f;
- uint32_t u[2];
+ float64 fd; /* ieee double precision */
+ float32 fs[2];/* ieee single precision */
+ uint64_t d; /* binary single fixed-point */
+ uint32_t w[2]; /* binary single fixed-point */
};
+/* define FP_ENDIAN_IDX to access the same location
+ * in the fpr_t union regardless of the host endianess
+ */
+#if defined(WORDS_BIGENDIAN)
+# define FP_ENDIAN_IDX 1
+#else
+# define FP_ENDIAN_IDX 0
+#endif
#if defined(MIPS_USES_R4K_TLB)
typedef struct tlb_t tlb_t;
struct tlb_t {
target_ulong VPN;
target_ulong end;
- uint8_t ASID;
- uint8_t G;
- uint8_t C[2];
- uint8_t V[2];
- uint8_t D[2];
+ target_ulong end2;
+ uint_fast8_t ASID;
+ uint_fast16_t G:1;
+ uint_fast16_t C0:3;
+ uint_fast16_t C1:3;
+ uint_fast16_t V0:1;
+ uint_fast16_t V1:1;
+ uint_fast16_t D0:1;
+ uint_fast16_t D1:1;
target_ulong PFN[2];
};
#endif
#if defined(MIPS_USES_FPU)
/* Floating point registers */
fpr_t fpr[16];
- /* Floating point special purpose registers */
+#define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
+#define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
+#define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
+#define FPR_D(cpu, n) (FPR(cpu, n)->d)
+#define FPR_W(cpu, n) (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX])
+
+#ifndef USE_HOST_FLOAT_REGS
+ fpr_t ft0;
+ fpr_t ft1;
+ fpr_t ft2;
+#endif
+ float_status fp_status;
+ /* fpu implementation/revision register */
uint32_t fcr0;
- uint32_t fcr25;
- uint32_t fcr26;
- uint32_t fcr28;
- uint32_t fcsr;
+ /* fcsr */
+ uint32_t fcr31;
+#define SET_FP_COND(reg) do { (reg) |= (1<<23); } while(0)
+#define CLEAR_FP_COND(reg) do { (reg) &= ~(1<<23); } while(0)
+#define IS_FP_COND_SET(reg) (((reg) & (1<<23)) != 0)
+#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
+#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
+#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
+#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0)
+#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v) << 7); } while(0)
+#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v) << 2); } while(0)
+#define FP_INEXACT 1
+#define FP_UNDERFLOW 2
+#define FP_OVERFLOW 4
+#define FP_DIV0 8
+#define FP_INVALID 16
+#define FP_UNIMPLEMENTED 32
+
#endif
#if defined(MIPS_USES_R4K_TLB)
- tlb_t tlb[16];
+ tlb_t tlb[MIPS_TLB_NB];
#endif
uint32_t CP0_index;
uint32_t CP0_random;
#define CP0St_CU1 29
#define CP0St_CU0 28
#define CP0St_RP 27
+#define CP0St_FR 26
#define CP0St_RE 25
#define CP0St_BEV 22
#define CP0St_TS 21
uint32_t CP0_ErrorEPC;
uint32_t CP0_DESAVE;
/* Qemu */
-#if defined (USE_HOST_FLOAT_REGS) && defined(MIPS_USES_FPU)
- double ft0, ft1, ft2;
-#endif
struct QEMUTimer *timer; /* Internal timer */
int interrupt_request;
jmp_buf jmp_env;
int user_mode_only; /* user mode only simulation */
uint32_t hflags; /* CPU State */
/* TMASK defines different execution modes */
-#define MIPS_HFLAGS_TMASK 0x00FF
+#define MIPS_HFLAG_TMASK 0x007F
#define MIPS_HFLAG_MODE 0x001F /* execution modes */
#define MIPS_HFLAG_UM 0x0001 /* user mode */
#define MIPS_HFLAG_ERL 0x0002 /* Error mode */
#define MIPS_HFLAG_DM 0x0008 /* Debug mode */
#define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
#define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
-#define MIPS_HFLAG_DS 0x0080 /* In / out of delay slot */
- /* Those flags keep the branch state if the translation is interrupted
- * between the branch instruction and the delay slot
- */
-#define MIPS_HFLAG_BMASK 0x0F00
-#define MIPS_HFLAG_B 0x0100 /* Unconditional branch */
-#define MIPS_HFLAG_BC 0x0200 /* Conditional branch */
-#define MIPS_HFLAG_BL 0x0400 /* Likely branch */
-#define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
+ /* If translation is interrupted between the branch instruction and
+ * the delay slot, record what type of branch it is so that we can
+ * resume translation properly. It might be possible to reduce
+ * this from three bits to two. */
+#define MIPS_HFLAG_BMASK 0x0380
+#define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
+#define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
+#define MIPS_HFLAG_BL 0x0180 /* Likely branch */
+#define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
target_ulong btarget; /* Jump / branch target */
int bcond; /* Branch condition (if needed) */
+ int halted; /* TRUE if the CPU is in suspend state */
+
CPU_COMMON
};
EXCP_IBE,
EXCP_DBp,
EXCP_SYSCALL,
- EXCP_BREAK,
- EXCP_CpU, /* 16 */
+ EXCP_BREAK, /* 16 */
+ EXCP_CpU,
EXCP_RI,
EXCP_OVERFLOW,
EXCP_TRAP,
EXCP_DDBS,
EXCP_DWATCH,
- EXCP_LAE, /* 22 */
- EXCP_SAE,
+ EXCP_LAE,
+ EXCP_SAE, /* 24 */
EXCP_LTLBL,
EXCP_TLBL,
EXCP_TLBS,
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