/*
* MIPS emulation helpers for qemu.
- *
+ *
* Copyright (c) 2004-2005 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
#include "cpu.h"
#include "exec-all.h"
-/* MIPS32 4K MMU emulation */
-#ifdef MIPS_USES_R4K_TLB
-static int map_address (CPUState *env, target_ulong *physical, int *prot,
+enum {
+ TLBRET_DIRTY = -4,
+ TLBRET_INVALID = -3,
+ TLBRET_NOMATCH = -2,
+ TLBRET_BADADDR = -1,
+ TLBRET_MATCH = 0
+};
+
+/* no MMU emulation */
+int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
target_ulong address, int rw, int access_type)
{
- tlb_t *tlb;
- target_ulong tag;
- uint8_t ASID;
- int i, n;
- int ret;
+ *physical = address;
+ *prot = PAGE_READ | PAGE_WRITE;
+ return TLBRET_MATCH;
+}
+
+/* fixed mapping MMU emulation */
+int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
+ target_ulong address, int rw, int access_type)
+{
+ if (address <= (int32_t)0x7FFFFFFFUL) {
+ if (!(env->CP0_Status & (1 << CP0St_ERL)))
+ *physical = address + 0x40000000UL;
+ else
+ *physical = address;
+ } else if (address <= (int32_t)0xBFFFFFFFUL)
+ *physical = address & 0x1FFFFFFF;
+ else
+ *physical = address;
+
+ *prot = PAGE_READ | PAGE_WRITE;
+ return TLBRET_MATCH;
+}
+
+/* MIPS32/MIPS64 R4000-style MMU emulation */
+int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
+ target_ulong address, int rw, int access_type)
+{
+ uint8_t ASID = env->CP0_EntryHi & 0xFF;
+ int i;
+
+ for (i = 0; i < env->tlb->tlb_in_use; i++) {
+ r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
+ /* 1k pages are not supported. */
+ target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
+ target_ulong tag = address & ~mask;
+ target_ulong VPN = tlb->VPN & ~mask;
+#ifdef TARGET_MIPS64
+ tag &= env->SEGMask;
+#endif
- ret = -2;
- tag = address & 0xFFFFE000;
- ASID = env->CP0_EntryHi & 0xFF;
- for (i = 0; i < MIPS_TLB_NB; i++) {
- tlb = &env->tlb[i];
/* Check ASID, virtual page number & size */
- if ((tlb->G == 1 || tlb->ASID == ASID) &&
- tlb->VPN == tag && address < tlb->end2) {
+ if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
/* TLB match */
- n = (address >> 12) & 1;
+ int n = !!(address & mask & ~(mask >> 1));
/* Check access rights */
- if (!(n ? tlb->V1 : tlb->V0))
- return -3;
- if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
- *physical = tlb->PFN[n] | (address & 0xFFF);
+ if (!(n ? tlb->V1 : tlb->V0))
+ return TLBRET_INVALID;
+ if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
+ *physical = tlb->PFN[n] | (address & (mask >> 1));
*prot = PAGE_READ;
if (n ? tlb->D1 : tlb->D0)
*prot |= PAGE_WRITE;
- return 0;
+ return TLBRET_MATCH;
}
- return -4;
+ return TLBRET_DIRTY;
}
}
-
- return ret;
+ return TLBRET_NOMATCH;
}
-#endif
-int get_physical_address (CPUState *env, target_ulong *physical, int *prot,
- target_ulong address, int rw, int access_type)
+static int get_physical_address (CPUState *env, target_ulong *physical,
+ int *prot, target_ulong address,
+ int rw, int access_type)
{
- int user_mode;
- int ret;
+ /* User mode can only access useg/xuseg */
+ int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
+#ifdef TARGET_MIPS64
+ int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
+ int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
+ int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
+#endif
+ int ret = TLBRET_MATCH;
- /* User mode can only access useg */
- user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
#if 0
if (logfile) {
fprintf(logfile, "user mode %d h %08x\n",
user_mode, env->hflags);
}
#endif
- if (user_mode && address > 0x7FFFFFFFUL)
- return -1;
- ret = 0;
- if (address < 0x80000000UL) {
- if (!(env->hflags & MIPS_HFLAG_ERL)) {
-#ifdef MIPS_USES_R4K_TLB
- ret = map_address(env, physical, prot, address, rw, access_type);
+
+#ifdef TARGET_MIPS64
+ if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
+ return TLBRET_BADADDR;
#else
- *physical = address + 0x40000000UL;
- *prot = PAGE_READ | PAGE_WRITE;
+ if (user_mode && address > 0x7FFFFFFFUL)
+ return TLBRET_BADADDR;
#endif
- } else {
- *physical = address;
+
+ if (address <= (int32_t)0x7FFFFFFFUL) {
+ /* useg */
+ if (env->CP0_Status & (1 << CP0St_ERL)) {
+ *physical = address & 0xFFFFFFFF;
*prot = PAGE_READ | PAGE_WRITE;
+ } else {
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ }
+#ifdef TARGET_MIPS64
+/*
+ XXX: Assuming :
+ - PABITS = 36 (correct for MIPS64R1)
+*/
+ } else if (address < 0x3FFFFFFFFFFFFFFFULL) {
+ /* xuseg */
+ if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ } else {
+ ret = TLBRET_BADADDR;
+ }
+ } else if (address < 0x7FFFFFFFFFFFFFFFULL) {
+ /* xsseg */
+ if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ } else {
+ ret = TLBRET_BADADDR;
}
- } else if (address < 0xA0000000UL) {
+ } else if (address < 0xBFFFFFFFFFFFFFFFULL) {
+ /* xkphys */
+ /* XXX: check supervisor mode */
+ if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
+ {
+ *physical = address & 0X0000000FFFFFFFFFULL;
+ *prot = PAGE_READ | PAGE_WRITE;
+ } else {
+ ret = TLBRET_BADADDR;
+ }
+ } else if (address < 0xFFFFFFFF7FFFFFFFULL) {
+ /* xkseg */
+ /* XXX: check supervisor mode */
+ if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ } else {
+ ret = TLBRET_BADADDR;
+ }
+#endif
+ } else if (address < (int32_t)0xA0000000UL) {
/* kseg0 */
/* XXX: check supervisor mode */
- *physical = address - 0x80000000UL;
+ *physical = address - (int32_t)0x80000000UL;
*prot = PAGE_READ | PAGE_WRITE;
- } else if (address < 0xC0000000UL) {
+ } else if (address < (int32_t)0xC0000000UL) {
/* kseg1 */
/* XXX: check supervisor mode */
- *physical = address - 0xA0000000UL;
+ *physical = address - (int32_t)0xA0000000UL;
*prot = PAGE_READ | PAGE_WRITE;
- } else if (address < 0xE0000000UL) {
+ } else if (address < (int32_t)0xE0000000UL) {
/* kseg2 */
-#ifdef MIPS_USES_R4K_TLB
- ret = map_address(env, physical, prot, address, rw, access_type);
-#else
- *physical = address;
- *prot = PAGE_READ | PAGE_WRITE;
-#endif
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
} else {
/* kseg3 */
/* XXX: check supervisor mode */
/* XXX: debug segment is not emulated */
-#ifdef MIPS_USES_R4K_TLB
- ret = map_address(env, physical, prot, address, rw, access_type);
-#else
- *physical = address;
- *prot = PAGE_READ | PAGE_WRITE;
-#endif
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
}
#if 0
if (logfile) {
- fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
- access_type, *physical, *prot, ret);
+ fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
+ address, rw, access_type, *physical, *prot, ret);
}
#endif
return ret;
}
-#if defined(CONFIG_USER_ONLY)
-target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+#if defined(CONFIG_USER_ONLY)
+target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
return addr;
}
#else
-target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
target_ulong phys_addr;
int prot;
#if 0
cpu_dump_state(env, logfile, fprintf, 0);
#endif
- fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
- __func__, env->PC, address, rw, is_user, is_softmmu);
+ fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
+ __func__, env->PC[env->current_tc], address, rw, is_user, is_softmmu);
}
rw &= 1;
access_type = ACCESS_INT;
if (env->user_mode_only) {
/* user mode only emulation */
- ret = -2;
+ ret = TLBRET_NOMATCH;
goto do_fault;
}
ret = get_physical_address(env, &physical, &prot,
address, rw, access_type);
if (logfile) {
- fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
+ fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
__func__, address, ret, physical, prot);
}
- if (ret == 0) {
- ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot,
- is_user, is_softmmu);
+ if (ret == TLBRET_MATCH) {
+ ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
+ physical & TARGET_PAGE_MASK, prot,
+ is_user, is_softmmu);
} else if (ret < 0) {
do_fault:
switch (ret) {
default:
- case -1:
+ case TLBRET_BADADDR:
/* Reference to kernel address from user mode or supervisor mode */
/* Reference to supervisor address from user mode */
if (rw)
else
exception = EXCP_AdEL;
break;
- case -2:
+ case TLBRET_NOMATCH:
/* No TLB match for a mapped address */
if (rw)
exception = EXCP_TLBS;
exception = EXCP_TLBL;
error_code = 1;
break;
- case -3:
+ case TLBRET_INVALID:
/* TLB match with no valid bit */
if (rw)
exception = EXCP_TLBS;
else
exception = EXCP_TLBL;
break;
- case -4:
+ case TLBRET_DIRTY:
/* TLB match but 'D' bit is cleared */
exception = EXCP_LTLBL;
break;
-
+
}
/* Raise exception */
env->CP0_BadVAddr = address;
- env->CP0_Context = (env->CP0_Context & 0xff800000) |
+ env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
((address >> 9) & 0x007ffff0);
env->CP0_EntryHi =
- (env->CP0_EntryHi & 0xFF) | (address & 0xFFFFE000);
+ (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
+#ifdef TARGET_MIPS64
+ env->CP0_EntryHi &= env->SEGMask;
+ env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
+ ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
+ ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
+#endif
env->exception_index = exception;
env->error_code = error_code;
ret = 1;
return ret;
}
+#if defined(CONFIG_USER_ONLY)
+void do_interrupt (CPUState *env)
+{
+ env->exception_index = EXCP_NONE;
+}
+#else
void do_interrupt (CPUState *env)
{
- target_ulong pc, offset;
+ target_ulong offset;
int cause = -1;
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
- fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
- __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
+ fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
+ __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index);
}
if (env->exception_index == EXCP_EXT_INTERRUPT &&
(env->hflags & MIPS_HFLAG_DM))
* (but we assume the pc has always been updated during
* code translation).
*/
- env->CP0_DEPC = env->PC;
+ env->CP0_DEPC = env->PC[env->current_tc];
goto enter_debug_mode;
case EXCP_DINT:
env->CP0_Debug |= 1 << CP0DB_DINT;
goto set_DEPC;
case EXCP_DDBL:
env->CP0_Debug |= 1 << CP0DB_DDBL;
- goto set_DEPC;
set_DEPC:
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
- * come back to the jump
- */
- env->CP0_DEPC = env->PC - 4;
+ come back to the jump. */
+ env->CP0_DEPC = env->PC[env->current_tc] - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
- env->CP0_DEPC = env->PC;
+ env->CP0_DEPC = env->PC[env->current_tc];
}
enter_debug_mode:
env->hflags |= MIPS_HFLAG_DM;
+ if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
+ env->hflags |= MIPS_HFLAG_64;
+ env->hflags &= ~MIPS_HFLAG_UM;
/* EJTAG probe trap enable is not implemented... */
- pc = 0xBFC00480;
+ if (!(env->CP0_Status & (1 << CP0St_EXL)))
+ env->CP0_Cause &= ~(1 << CP0Ca_BD);
+ env->PC[env->current_tc] = (int32_t)0xBFC00480;
break;
case EXCP_RESET:
-#ifdef MIPS_USES_R4K_TLB
- env->CP0_random = MIPS_TLB_NB - 1;
-#endif
- env->CP0_Wired = 0;
- env->CP0_Config0 = MIPS_CONFIG0;
-#if defined (MIPS_CONFIG1)
- env->CP0_Config1 = MIPS_CONFIG1;
-#endif
-#if defined (MIPS_CONFIG2)
- env->CP0_Config2 = MIPS_CONFIG2;
-#endif
-#if defined (MIPS_CONFIG3)
- env->CP0_Config3 = MIPS_CONFIG3;
-#endif
- env->CP0_WatchLo = 0;
- env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
- goto set_error_EPC;
+ cpu_reset(env);
+ break;
case EXCP_SRESET:
- env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
- (1 << CP0St_SR);
- env->CP0_WatchLo = 0;
+ env->CP0_Status |= (1 << CP0St_SR);
+ memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
goto set_error_EPC;
case EXCP_NMI:
- env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
- (1 << CP0St_NMI);
+ env->CP0_Status |= (1 << CP0St_NMI);
set_error_EPC:
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
- * come back to the jump
- */
- env->CP0_ErrorEPC = env->PC - 4;
+ come back to the jump. */
+ env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
- env->CP0_ErrorEPC = env->PC;
+ env->CP0_ErrorEPC = env->PC[env->current_tc];
}
- env->hflags = MIPS_HFLAG_ERL;
- pc = 0xBFC00000;
+ env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
+ if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
+ env->hflags |= MIPS_HFLAG_64;
+ env->hflags &= ~MIPS_HFLAG_UM;
+ if (!(env->CP0_Status & (1 << CP0St_EXL)))
+ env->CP0_Cause &= ~(1 << CP0Ca_BD);
+ env->PC[env->current_tc] = (int32_t)0xBFC00000;
break;
case EXCP_MCHECK:
cause = 24;
/* XXX: TODO: manage defered watch exceptions */
goto set_EPC;
case EXCP_AdEL:
- case EXCP_AdES:
cause = 4;
goto set_EPC;
+ case EXCP_AdES:
+ cause = 5;
+ goto set_EPC;
case EXCP_TLBL:
cause = 2;
- if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
- offset = 0x000;
+ if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
+#ifdef TARGET_MIPS64
+ int R = env->CP0_BadVAddr >> 62;
+ int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
+ int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
+ int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
+
+ if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
+ offset = 0x080;
+ else
+#endif
+ offset = 0x000;
+ }
goto set_EPC;
case EXCP_IBE:
cause = 6;
goto set_EPC;
case EXCP_CpU:
cause = 11;
- env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
+ env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
+ (env->error_code << CP0Ca_CE);
goto set_EPC;
case EXCP_OVERFLOW:
cause = 12;
case EXCP_TRAP:
cause = 13;
goto set_EPC;
+ case EXCP_FPE:
+ cause = 15;
+ goto set_EPC;
case EXCP_LTLBL:
cause = 1;
goto set_EPC;
case EXCP_TLBS:
cause = 3;
- if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
- offset = 0x000;
goto set_EPC;
+ case EXCP_THREAD:
+ cause = 25;
+ if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
+#ifdef TARGET_MIPS64
+ int R = env->CP0_BadVAddr >> 62;
+ int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
+ int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
+ int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
+
+ if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
+ offset = 0x080;
+ else
+#endif
+ offset = 0x000;
+ }
set_EPC:
- if (env->CP0_Status & (1 << CP0St_BEV)) {
- pc = 0xBFC00200;
- } else {
- pc = 0x80000000;
+ if (!(env->CP0_Status & (1 << CP0St_EXL))) {
+ if (env->hflags & MIPS_HFLAG_BMASK) {
+ /* If the exception was raised from a delay slot,
+ come back to the jump. */
+ env->CP0_EPC = env->PC[env->current_tc] - 4;
+ env->CP0_Cause |= (1 << CP0Ca_BD);
+ } else {
+ env->CP0_EPC = env->PC[env->current_tc];
+ env->CP0_Cause &= ~(1 << CP0Ca_BD);
+ }
+ env->CP0_Status |= (1 << CP0St_EXL);
+ if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
+ env->hflags |= MIPS_HFLAG_64;
+ env->hflags &= ~MIPS_HFLAG_UM;
}
- env->hflags |= MIPS_HFLAG_EXL;
- pc += offset;
- env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
- if (env->hflags & MIPS_HFLAG_BMASK) {
- /* If the exception was raised from a delay slot,
- * come back to the jump
- */
- env->CP0_EPC = env->PC - 4;
- env->CP0_Cause |= 0x80000000;
- env->hflags &= ~MIPS_HFLAG_BMASK;
+ env->hflags &= ~MIPS_HFLAG_BMASK;
+ if (env->CP0_Status & (1 << CP0St_BEV)) {
+ env->PC[env->current_tc] = (int32_t)0xBFC00200;
} else {
- env->CP0_EPC = env->PC;
- env->CP0_Cause &= ~0x80000000;
+ env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
}
+ env->PC[env->current_tc] += offset;
+ env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
break;
default:
if (logfile) {
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
exit(1);
}
- env->PC = pc;
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
- fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
- " S %08x C %08x A %08x D %08x\n",
- __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
+ fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
+ " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
+ __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index,
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
env->CP0_DEPC);
}
env->exception_index = EXCP_NONE;
}
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
+{
+ r4k_tlb_t *tlb;
+ target_ulong addr;
+ target_ulong end;
+ uint8_t ASID = env->CP0_EntryHi & 0xFF;
+ target_ulong mask;
+
+ tlb = &env->tlb->mmu.r4k.tlb[idx];
+ /* The qemu TLB is flushed when the ASID changes, so no need to
+ flush these entries again. */
+ if (tlb->G == 0 && tlb->ASID != ASID) {
+ return;
+ }
+
+ if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
+ /* For tlbwr, we can shadow the discarded entry into
+ a new (fake) TLB entry, as long as the guest can not
+ tell that it's there. */
+ env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
+ env->tlb->tlb_in_use++;
+ return;
+ }
+
+ /* 1k pages are not supported. */
+ mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
+ if (tlb->V0) {
+ addr = tlb->VPN & ~mask;
+#ifdef TARGET_MIPS64
+ if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
+ addr |= 0x3FFFFF0000000000ULL;
+ }
+#endif
+ end = addr | (mask >> 1);
+ while (addr < end) {
+ tlb_flush_page (env, addr);
+ addr += TARGET_PAGE_SIZE;
+ }
+ }
+ if (tlb->V1) {
+ addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
+#ifdef TARGET_MIPS64
+ if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
+ addr |= 0x3FFFFF0000000000ULL;
+ }
+#endif
+ end = addr | mask;
+ while (addr < end) {
+ tlb_flush_page (env, addr);
+ addr += TARGET_PAGE_SIZE;
+ }
+ }
+}
projects / mirror_qemu.git / blobdiff