/*
* MIPS emulation helpers for qemu.
- *
+ *
* Copyright (c) 2004-2005 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
uint8_t ASID = env->CP0_EntryHi & 0xFF;
int i;
- for (i = 0; i < env->tlb_in_use; i++) {
- r4k_tlb_t *tlb = &env->mmu.r4k.tlb[i];
+ for (i = 0; i < env->tlb->tlb_in_use; i++) {
+ r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
/* 1k pages are not supported. */
target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
target_ulong tag = address & ~mask;
target_ulong VPN = tlb->VPN & ~mask;
#ifdef TARGET_MIPS64
- tag &= 0xC00000FFFFFFFFFFULL;
+ tag &= env->SEGMask;
#endif
/* Check ASID, virtual page number & size */
if (address <= (int32_t)0x7FFFFFFFUL) {
/* useg */
- if (!(env->CP0_Status & (1 << CP0St_ERL) && user_mode)) {
- ret = env->map_address(env, physical, prot, address, rw, access_type);
- } else {
+ if (env->CP0_Status & (1 << CP0St_ERL)) {
*physical = address & 0xFFFFFFFF;
*prot = PAGE_READ | PAGE_WRITE;
+ } else {
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
}
#ifdef TARGET_MIPS64
/*
XXX: Assuming :
- PABITS = 36 (correct for MIPS64R1)
- - SEGBITS = 40
*/
} else if (address < 0x3FFFFFFFFFFFFFFFULL) {
/* xuseg */
- if (UX && address < 0x000000FFFFFFFFFFULL) {
- ret = env->map_address(env, physical, prot, address, rw, access_type);
+ if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
} else if (address < 0x7FFFFFFFFFFFFFFFULL) {
/* xsseg */
- if (SX && address < 0x400000FFFFFFFFFFULL) {
- ret = env->map_address(env, physical, prot, address, rw, access_type);
+ if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
} else if (address < 0xBFFFFFFFFFFFFFFFULL) {
/* xkphys */
/* XXX: check supervisor mode */
- if (KX && (address & 0x03FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
+ if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
{
- *physical = address & 0X000000FFFFFFFFFFULL;
+ *physical = address & 0X0000000FFFFFFFFFULL;
*prot = PAGE_READ | PAGE_WRITE;
} else {
ret = TLBRET_BADADDR;
} else if (address < 0xFFFFFFFF7FFFFFFFULL) {
/* xkseg */
/* XXX: check supervisor mode */
- if (KX && address < 0xC00000FF7FFFFFFFULL) {
- ret = env->map_address(env, physical, prot, address, rw, access_type);
+ if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
*prot = PAGE_READ | PAGE_WRITE;
} else if (address < (int32_t)0xE0000000UL) {
/* kseg2 */
- ret = env->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
} else {
/* kseg3 */
/* XXX: check supervisor mode */
/* XXX: debug segment is not emulated */
- ret = env->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
}
#if 0
if (logfile) {
return ret;
}
-#if defined(CONFIG_USER_ONLY)
+#if defined(CONFIG_USER_ONLY)
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
return addr;
cpu_dump_state(env, logfile, fprintf, 0);
#endif
fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
- __func__, env->PC, address, rw, is_user, is_softmmu);
+ __func__, env->PC[env->current_tc], address, rw, is_user, is_softmmu);
}
rw &= 1;
/* TLB match but 'D' bit is cleared */
exception = EXCP_LTLBL;
break;
-
+
}
/* Raise exception */
env->CP0_BadVAddr = address;
env->CP0_EntryHi =
(env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
#ifdef TARGET_MIPS64
- env->CP0_EntryHi &= 0xc00000ffffffffffULL;
- env->CP0_XContext = (env->CP0_XContext & 0xfffffffe00000000ULL) |
- ((address >> 31) & 0x0000000180000000ULL) |
- ((address >> 9) & 0x000000007ffffff0ULL);
+ env->CP0_EntryHi &= env->SEGMask;
+ env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
+ ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
+ ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
#endif
env->exception_index = exception;
env->error_code = error_code;
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
- __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
+ __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index);
}
if (env->exception_index == EXCP_EXT_INTERRUPT &&
(env->hflags & MIPS_HFLAG_DM))
* (but we assume the pc has always been updated during
* code translation).
*/
- env->CP0_DEPC = env->PC;
+ env->CP0_DEPC = env->PC[env->current_tc];
goto enter_debug_mode;
case EXCP_DINT:
env->CP0_Debug |= 1 << CP0DB_DINT;
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
- env->CP0_DEPC = env->PC - 4;
+ env->CP0_DEPC = env->PC[env->current_tc] - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
- env->CP0_DEPC = env->PC;
+ env->CP0_DEPC = env->PC[env->current_tc];
}
enter_debug_mode:
env->hflags |= MIPS_HFLAG_DM;
- env->hflags |= MIPS_HFLAG_64;
+ if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
+ env->hflags |= MIPS_HFLAG_64;
env->hflags &= ~MIPS_HFLAG_UM;
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
- env->PC = (int32_t)0xBFC00480;
+ env->PC[env->current_tc] = (int32_t)0xBFC00480;
break;
case EXCP_RESET:
cpu_reset(env);
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
- env->CP0_ErrorEPC = env->PC - 4;
+ env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
- env->CP0_ErrorEPC = env->PC;
+ env->CP0_ErrorEPC = env->PC[env->current_tc];
}
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
- env->hflags |= MIPS_HFLAG_64;
+ if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
+ env->hflags |= MIPS_HFLAG_64;
env->hflags &= ~MIPS_HFLAG_UM;
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
- env->PC = (int32_t)0xBFC00000;
+ env->PC[env->current_tc] = (int32_t)0xBFC00000;
break;
case EXCP_MCHECK:
cause = 24;
goto set_EPC;
case EXCP_TLBS:
cause = 3;
+ goto set_EPC;
+ case EXCP_THREAD:
+ cause = 25;
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
#ifdef TARGET_MIPS64
int R = env->CP0_BadVAddr >> 62;
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
- env->CP0_EPC = env->PC - 4;
+ env->CP0_EPC = env->PC[env->current_tc] - 4;
env->CP0_Cause |= (1 << CP0Ca_BD);
} else {
- env->CP0_EPC = env->PC;
+ env->CP0_EPC = env->PC[env->current_tc];
env->CP0_Cause &= ~(1 << CP0Ca_BD);
}
env->CP0_Status |= (1 << CP0St_EXL);
- env->hflags |= MIPS_HFLAG_64;
+ if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
+ env->hflags |= MIPS_HFLAG_64;
env->hflags &= ~MIPS_HFLAG_UM;
}
env->hflags &= ~MIPS_HFLAG_BMASK;
if (env->CP0_Status & (1 << CP0St_BEV)) {
- env->PC = (int32_t)0xBFC00200;
+ env->PC[env->current_tc] = (int32_t)0xBFC00200;
} else {
- env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
+ env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
}
- env->PC += offset;
+ env->PC[env->current_tc] += offset;
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
break;
default:
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
- __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
+ __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index,
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
env->CP0_DEPC);
}
uint8_t ASID = env->CP0_EntryHi & 0xFF;
target_ulong mask;
- tlb = &env->mmu.r4k.tlb[idx];
+ tlb = &env->tlb->mmu.r4k.tlb[idx];
/* The qemu TLB is flushed when the ASID changes, so no need to
flush these entries again. */
if (tlb->G == 0 && tlb->ASID != ASID) {
return;
}
- if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
+ if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
/* For tlbwr, we can shadow the discarded entry into
a new (fake) TLB entry, as long as the guest can not
tell that it's there. */
- env->mmu.r4k.tlb[env->tlb_in_use] = *tlb;
- env->tlb_in_use++;
+ env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
+ env->tlb->tlb_in_use++;
return;
}
if (tlb->V0) {
addr = tlb->VPN & ~mask;
#ifdef TARGET_MIPS64
- if (addr >= 0xC00000FF80000000ULL) {
+ if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
addr |= 0x3FFFFF0000000000ULL;
}
#endif
if (tlb->V1) {
addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
#ifdef TARGET_MIPS64
- if (addr >= 0xC00000FF80000000ULL) {
+ if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
addr |= 0x3FFFFF0000000000ULL;
}
#endif
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