Revert "Get rid of _t suffix"

[mirror_qemu.git] / target-mips / translate.c

diff --git a/target-mips/translate.c b/target-mips/translate.c
index aabb69c2df6c74d3de62170612e3c226bda13c8f..58f483fa0a0dddd1be35e77b1bcc79a314b29fb5 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -187,10 +187,10 @@ enum {
     OPC_MOVCI    = 0x01 | OPC_SPECIAL,
 
     /* Special */
-    OPC_PMON     = 0x05 | OPC_SPECIAL, /* inofficial */
+    OPC_PMON     = 0x05 | OPC_SPECIAL, /* unofficial */
     OPC_SYSCALL  = 0x0C | OPC_SPECIAL,
     OPC_BREAK    = 0x0D | OPC_SPECIAL,
-    OPC_SPIM     = 0x0E | OPC_SPECIAL, /* inofficial */
+    OPC_SPIM     = 0x0E | OPC_SPECIAL, /* unofficial */
     OPC_SYNC     = 0x0F | OPC_SPECIAL,
 
     OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,
@@ -803,9 +803,9 @@ generate_exception (DisasContext *ctx, int excp)
 }
 
 /* Addresses computation */
-static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1)
+static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
 {
-    tcg_gen_add_tl(t0, t0, t1);
+    tcg_gen_add_tl(ret, arg0, arg1);
 
 #if defined(TARGET_MIPS64)
     /* For compatibility with 32-bit code, data reference in user mode
@@ -813,7 +813,7 @@ static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1)
        See the MIPS64 PRA manual, section 4.10. */
     if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
         !(ctx->hflags & MIPS_HFLAG_UX)) {
-        tcg_gen_ext32s_i64(t0, t0);
+        tcg_gen_ext32s_i64(ret, ret);
     }
 #endif
 }
@@ -1005,7 +1005,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
         gen_load_gpr(t0, base);
     } else {
         tcg_gen_movi_tl(t0, offset);
-        gen_op_addr_add(ctx, t0, cpu_gpr[base]);
+        gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */
@@ -1163,7 +1163,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
         gen_load_gpr(t0, base);
     } else {
         tcg_gen_movi_tl(t0, offset);
-        gen_op_addr_add(ctx, t0, cpu_gpr[base]);
+        gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */
@@ -1202,7 +1202,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
         gen_load_gpr(t0, base);
     } else {
         tcg_gen_movi_tl(t0, offset);
-        gen_op_addr_add(ctx, t0, cpu_gpr[base]);
+        gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */
@@ -7264,7 +7264,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
         gen_load_gpr(t0, base);
     } else {
         gen_load_gpr(t0, index);
-        gen_op_addr_add(ctx, t0, cpu_gpr[base]);
+        gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */
@@ -7660,6 +7660,10 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
         gen_goto_tb(ctx, 1, ctx->pc + 4);
         gen_set_label(l1);
     }
+
+    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
+        tcg_gen_debug_insn_start(ctx->pc);
+
     op = MASK_OP_MAJOR(ctx->opcode);
     rs = (ctx->opcode >> 21) & 0x1f;
     rt = (ctx->opcode >> 16) & 0x1f;