MMU_TYPE_R8000
};
-struct mips_def_t {
+struct mips_def {
const char *name;
int32_t CP0_PRid;
int32_t CP0_Config0;
/*****************************************************************************/
/* MIPS CPU definitions */
-static const mips_def_t mips_defs[] =
+static const a_mips_def mips_defs[] =
{
{
.name = "4Kc",
#endif
};
-static const mips_def_t *cpu_mips_find_by_name (const char *name)
+static const a_mips_def *cpu_mips_find_by_name (const char *name)
{
int i;
}
#ifndef CONFIG_USER_ONLY
-static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void no_mmu_init (CPUMIPSState *env, const a_mips_def *def)
{
env->tlb->nb_tlb = 1;
env->tlb->map_address = &no_mmu_map_address;
}
-static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void fixed_mmu_init (CPUMIPSState *env, const a_mips_def *def)
{
env->tlb->nb_tlb = 1;
env->tlb->map_address = &fixed_mmu_map_address;
}
-static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void r4k_mmu_init (CPUMIPSState *env, const a_mips_def *def)
{
env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
env->tlb->map_address = &r4k_map_address;
env->tlb->helper_tlbr = r4k_helper_tlbr;
}
-static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void mmu_init (CPUMIPSState *env, const a_mips_def *def)
{
env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
}
#endif /* CONFIG_USER_ONLY */
-static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
+static void fpu_init (CPUMIPSState *env, const a_mips_def *def)
{
int i;
#endif
}
-static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
+static void mvp_init (CPUMIPSState *env, const a_mips_def *def)
{
env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
(0x1 << CP0MVPC1_PCP1);
}
-static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
+static int cpu_mips_register (CPUMIPSState *env, const a_mips_def *def)
{
env->CP0_PRid = def->CP0_PRid;
env->CP0_Config0 = def->CP0_Config0;