* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "disas/disas.h"
#include "tcg-op.h"
#include "qemu-common.h"
#include "qemu/log.h"
-#include "config.h"
#include "qemu/bitops.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
+#include "trace-tcg.h"
+#include "exec/log.h"
+
+
#define OPENRISC_DISAS
#ifdef OPENRISC_DISAS
uint32_t delayed_branch;
} DisasContext;
-static TCGv_ptr cpu_env;
+static TCGv_env cpu_env;
static TCGv cpu_sr;
static TCGv cpu_R[32];
static TCGv cpu_pc;
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- cpu_sr = tcg_global_mem_new(TCG_AREG0,
+ tcg_ctx.tcg_env = cpu_env;
+ cpu_sr = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, sr), "sr");
- env_flags = tcg_global_mem_new_i32(TCG_AREG0,
+ env_flags = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUOpenRISCState, flags),
"flags");
- cpu_pc = tcg_global_mem_new(TCG_AREG0,
+ cpu_pc = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, pc), "pc");
- cpu_npc = tcg_global_mem_new(TCG_AREG0,
+ cpu_npc = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, npc), "npc");
- cpu_ppc = tcg_global_mem_new(TCG_AREG0,
+ cpu_ppc = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, ppc), "ppc");
- jmp_pc = tcg_global_mem_new(TCG_AREG0,
+ jmp_pc = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
- env_btaken = tcg_global_mem_new_i32(TCG_AREG0,
+ env_btaken = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUOpenRISCState, btaken),
"btaken");
- fpcsr = tcg_global_mem_new_i32(TCG_AREG0,
+ fpcsr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUOpenRISCState, fpcsr),
"fpcsr");
- machi = tcg_global_mem_new(TCG_AREG0,
+ machi = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, machi),
"machi");
- maclo = tcg_global_mem_new(TCG_AREG0,
+ maclo = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, maclo),
"maclo");
- fpmaddhi = tcg_global_mem_new(TCG_AREG0,
+ fpmaddhi = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, fpmaddhi),
"fpmaddhi");
- fpmaddlo = tcg_global_mem_new(TCG_AREG0,
+ fpmaddlo = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, fpmaddlo),
"fpmaddlo");
for (i = 0; i < 32; i++) {
- cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
+ cpu_R[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, gpr[i]),
regnames[i]);
}
/* Writeback SR_F translation space to execution space. */
static inline void wb_SR_F(void)
{
- int label;
-
- label = gen_new_label();
+ TCGLabel *label = gen_new_label();
tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label);
tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
}
#endif*/
+static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
+{
+ if (unlikely(dc->singlestep_enabled)) {
+ return false;
+ }
+
+#ifndef CONFIG_USER_ONLY
+ return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
+#else
+ return true;
+#endif
+}
+
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
{
- TranslationBlock *tb;
- tb = dc->tb;
- if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
- likely(!dc->singlestep_enabled)) {
+ if (use_goto_tb(dc, dest)) {
tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_goto_tb(n);
- tcg_gen_exit_tb((uintptr_t)tb + n);
+ tcg_gen_exit_tb((uintptr_t)dc->tb + n);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
if (dc->singlestep_enabled) {
case 0x03: /* l.bnf */
case 0x04: /* l.bf */
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv sr_f = tcg_temp_new();
tcg_gen_movi_tl(jmp_pc, dc->pc+8);
tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
case 0x00: /* l.add */
LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 tb = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
tcg_gen_add_i64(td, ta, tb);
- tcg_gen_trunc_i64_i32(res, td);
+ tcg_gen_extrl_i64_i32(res, td);
tcg_gen_shri_i64(td, td, 31);
tcg_gen_andi_i64(td, td, 0x3);
/* Jump to lab when no overflow. */
case 0x00:
LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 tb = tcg_temp_new_i64();
TCGv_i64 tcy = tcg_temp_local_new_i64();
tcg_gen_shri_i64(tcy, tcy, 10);
tcg_gen_add_i64(td, ta, tb);
tcg_gen_add_i64(td, td, tcy);
- tcg_gen_trunc_i64_i32(res, td);
+ tcg_gen_extrl_i64_i32(res, td);
tcg_gen_shri_i64(td, td, 32);
tcg_gen_andi_i64(td, td, 0x3);
/* Jump to lab when no overflow. */
case 0x00:
LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 tb = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
tcg_gen_sub_i64(td, ta, tb);
- tcg_gen_trunc_i64_i32(res, td);
+ tcg_gen_extrl_i64_i32(res, td);
tcg_gen_shri_i64(td, td, 31);
tcg_gen_andi_i64(td, td, 0x3);
/* Jump to lab when no overflow. */
case 0x03: /* l.div */
LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab0 = gen_new_label();
- int lab1 = gen_new_label();
- int lab2 = gen_new_label();
- int lab3 = gen_new_label();
+ TCGLabel *lab0 = gen_new_label();
+ TCGLabel *lab1 = gen_new_label();
+ TCGLabel *lab2 = gen_new_label();
+ TCGLabel *lab3 = gen_new_label();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
if (rb == 0) {
tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
case 0x03: /* l.divu */
LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab0 = gen_new_label();
- int lab1 = gen_new_label();
- int lab2 = gen_new_label();
+ TCGLabel *lab0 = gen_new_label();
+ TCGLabel *lab1 = gen_new_label();
+ TCGLabel *lab2 = gen_new_label();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
if (rb == 0) {
tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
TCGv_i64 trb = tcg_temp_local_new_i64();
TCGv_i64 high = tcg_temp_new_i64();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- int lab = gen_new_label();
- /* Calculate the each result. */
+ TCGLabel *lab = gen_new_label();
+ /* Calculate each result. */
tcg_gen_extu_i32_i64(tra, cpu_R[ra]);
tcg_gen_extu_i32_i64(trb, cpu_R[rb]);
tcg_gen_mul_i64(result, tra, trb);
tcg_temp_free_i64(tra);
tcg_temp_free_i64(trb);
tcg_gen_shri_i64(high, result, TARGET_LONG_BITS);
- /* Overflow or not. */
+ /* Overflow or not. */
tcg_gen_brcondi_i64(TCG_COND_EQ, high, 0x00000000, lab);
tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
case 0x00: /* l.cmov */
LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb);
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv res = tcg_temp_local_new();
TCGv sr_f = tcg_temp_new();
tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
tcg_gen_ext_i32_i64(t1, dst);
tcg_gen_concat_i32_i64(t2, maclo, machi);
tcg_gen_add_i64(t2, t2, t1);
- tcg_gen_trunc_i64_i32(maclo, t2);
+ tcg_gen_extrl_i64_i32(maclo, t2);
tcg_gen_shri_i64(t2, t2, 32);
- tcg_gen_trunc_i64_i32(machi, t2);
+ tcg_gen_extrl_i64_i32(machi, t2);
tcg_temp_free_i32(dst);
tcg_temp_free(ttmp);
tcg_temp_free_i64(t1);
if (I16 == 0) {
tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
} else {
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
TCGv_i32 res = tcg_temp_local_new_i32();
TCGv_i32 sr_ove = tcg_temp_local_new_i32();
tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
- tcg_gen_trunc_i64_i32(res, td);
+ tcg_gen_extrl_i64_i32(res, td);
tcg_gen_shri_i64(td, td, 32);
tcg_gen_andi_i64(td, td, 0x3);
/* Jump to lab when no overflow. */
case 0x28: /* l.addic */
LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16);
{
- int lab = gen_new_label();
+ TCGLabel *lab = gen_new_label();
TCGv_i64 ta = tcg_temp_new_i64();
TCGv_i64 td = tcg_temp_local_new_i64();
TCGv_i64 tcy = tcg_temp_local_new_i64();
tcg_gen_extu_i32_i64(tcy, sr_cy);
tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
tcg_gen_add_i64(td, td, tcy);
- tcg_gen_trunc_i64_i32(res, td);
+ tcg_gen_extrl_i64_i32(res, td);
tcg_gen_shri_i64(td, td, 32);
tcg_gen_andi_i64(td, td, 0x3);
/* Jump to lab when no overflow. */
tcg_gen_ext_i32_i64(t1, t0);
tcg_gen_concat_i32_i64(t2, maclo, machi);
tcg_gen_add_i64(t2, t2, t1);
- tcg_gen_trunc_i64_i32(maclo, t2);
+ tcg_gen_extrl_i64_i32(maclo, t2);
tcg_gen_shri_i64(t2, t2, 32);
- tcg_gen_trunc_i64_i32(machi, t2);
+ tcg_gen_extrl_i64_i32(machi, t2);
tcg_temp_free_i32(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
tcg_gen_ext_i32_i64(t1, t0);
tcg_gen_concat_i32_i64(t2, maclo, machi);
tcg_gen_sub_i64(t2, t2, t1);
- tcg_gen_trunc_i64_i32(maclo, t2);
+ tcg_gen_extrl_i64_i32(maclo, t2);
tcg_gen_shri_i64(t2, t2, 32);
- tcg_gen_trunc_i64_i32(machi, t2);
+ tcg_gen_extrl_i64_i32(machi, t2);
tcg_temp_free_i32(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
#ifdef OPENRISC_DISAS
uint32_t K16;
#endif
- op0 = extract32(insn, 16, 8);
+ op0 = extract32(insn, 16, 10);
#ifdef OPENRISC_DISAS
K16 = extract32(insn, 0, 16);
#endif
}
}
-static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc)
-{
- CPUState *cs = CPU(cpu);
- CPUBreakpoint *bp;
-
- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
- if (bp->pc == dc->pc) {
- tcg_gen_movi_tl(cpu_pc, dc->pc);
- gen_exception(dc, EXCP_DEBUG);
- dc->is_jmp = DISAS_UPDATE;
- }
- }
- }
-}
-
-static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
- TranslationBlock *tb,
- int search_pc)
+void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
{
+ OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
struct DisasContext ctx, *dc = &ctx;
- uint16_t *gen_opc_end;
uint32_t pc_start;
- int j, k;
uint32_t next_page_start;
int num_insns;
int max_insns;
pc_start = tb->pc;
dc->tb = tb;
- gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
dc->is_jmp = DISAS_NEXT;
dc->ppc = pc_start;
dc->pc = pc_start;
dc->flags = cpu->env.cpucfgr;
- dc->mem_idx = cpu_mmu_index(&cpu->env);
+ dc->mem_idx = cpu_mmu_index(&cpu->env, false);
dc->synced_flags = dc->tb_flags = tb->flags;
dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
dc->singlestep_enabled = cs->singlestep_enabled;
}
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
- k = -1;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
}
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
+ }
- gen_tb_start();
+ gen_tb_start(tb);
do {
- check_breakpoint(cpu, dc);
- if (search_pc) {
- j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
- if (k < j) {
- k++;
- while (k < j) {
- tcg_ctx.gen_opc_instr_start[k++] = 0;
- }
- }
- tcg_ctx.gen_opc_pc[k] = dc->pc;
- tcg_ctx.gen_opc_instr_start[k] = 1;
- tcg_ctx.gen_opc_icount[k] = num_insns;
- }
+ tcg_gen_insn_start(dc->pc);
+ num_insns++;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
- tcg_gen_debug_insn_start(dc->pc);
+ if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
+ tcg_gen_movi_tl(cpu_pc, dc->pc);
+ gen_exception(dc, EXCP_DEBUG);
+ dc->is_jmp = DISAS_UPDATE;
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ dc->pc += 4;
+ break;
}
- if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
+ if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}
dc->ppc = dc->pc - 4;
tcg_gen_movi_tl(cpu_npc, dc->npc);
disas_openrisc_insn(dc, cpu);
dc->pc = dc->npc;
- num_insns++;
/* delay slot */
if (dc->delayed_branch) {
dc->delayed_branch--;
}
}
} while (!dc->is_jmp
- && tcg_ctx.gen_opc_ptr < gen_opc_end
+ && !tcg_op_buf_full()
&& !cs->singlestep_enabled
&& !singlestep
&& (dc->pc < next_page_start)
}
gen_tb_end(tb, num_insns);
- *tcg_ctx.gen_opc_ptr = INDEX_op_end;
- if (search_pc) {
- j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
- k++;
- while (k <= j) {
- tcg_ctx.gen_opc_instr_start[k++] = 0;
- }
- } else {
- tb->size = dc->pc - pc_start;
- tb->icount = num_insns;
- }
+
+ tb->size = dc->pc - pc_start;
+ tb->icount = num_insns;
#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
+ && qemu_log_in_addr_range(pc_start)) {
qemu_log("\n");
- log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0);
- qemu_log("\nisize=%d osize=%td\n",
- dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
- tcg_ctx.gen_opc_buf);
+ log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
+ qemu_log("\nisize=%d osize=%d\n",
+ dc->pc - pc_start, tcg_op_buf_count());
}
#endif
}
-void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
-{
- gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 0);
-}
-
-void gen_intermediate_code_pc(CPUOpenRISCState *env,
- struct TranslationBlock *tb)
-{
- gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 1);
-}
-
void openrisc_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
int flags)
}
void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb,
- int pc_pos)
+ target_ulong *data)
{
- env->pc = tcg_ctx.gen_opc_pc[pc_pos];
+ env->pc = data[0];
}
projects / mirror_qemu.git / blobdiff