{
int i;
+ if (env->cc_op > 3) {
+ cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
+ env->psw.mask, env->psw.addr, cc_name(env->cc_op));
+ } else {
+ cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
+ env->psw.mask, env->psw.addr, env->cc_op);
+ }
+
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
if ((i % 4) == 3) {
}
}
- cpu_fprintf(f, "\n");
-
#ifndef CONFIG_USER_ONLY
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
}
#endif
- cpu_fprintf(f, "\n");
-
- if (env->cc_op > 3) {
- cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
- env->psw.mask, env->psw.addr, cc_name(env->cc_op));
- } else {
- cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
- env->psw.mask, env->psw.addr, env->cc_op);
- }
-
#ifdef DEBUG_INLINE_BRANCHES
for (i = 0; i < CC_OP_MAX; i++) {
cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
inline_branch_miss[i], inline_branch_hit[i]);
}
#endif
+
+ cpu_fprintf(f, "\n");
}
static TCGv_i64 psw_addr;
#endif
}
-static inline uint64_t ld_code2(uint64_t pc)
+static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
{
- return (uint64_t)lduw_code(pc);
+ return (uint64_t)cpu_lduw_code(env, pc);
}
-static inline uint64_t ld_code4(uint64_t pc)
+static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
{
- return (uint64_t)ldl_code(pc);
+ return (uint64_t)cpu_ldl_code(env, pc);
}
-static inline uint64_t ld_code6(uint64_t pc)
+static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
{
uint64_t opc;
- opc = (uint64_t)lduw_code(pc) << 32;
- opc |= (uint64_t)(uint32_t)ldl_code(pc+2);
+ opc = (uint64_t)cpu_lduw_code(env, pc) << 32;
+ opc |= (uint64_t)(uint32_t)cpu_ldl_code(env, pc + 2);
return opc;
}
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
update_psw_addr(s);
gen_op_calc_cc(s);
- gen_helper_exception(tmp);
+ gen_helper_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
s->is_jmp = DISAS_EXCP;
}
#ifdef CONFIG_USER_ONLY
-static void gen_illegal_opcode(DisasContext *s, int ilc)
+static void gen_illegal_opcode(CPUS390XState *env, DisasContext *s, int ilc)
{
TCGv_i32 tmp = tcg_const_i32(EXCP_SPEC);
update_psw_addr(s);
gen_op_calc_cc(s);
- gen_helper_exception(tmp);
+ gen_helper_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
s->is_jmp = DISAS_EXCP;
}
#else /* CONFIG_USER_ONLY */
-static void debug_print_inst(DisasContext *s, int ilc)
+static void debug_print_inst(CPUS390XState *env, DisasContext *s, int ilc)
{
#ifdef DEBUG_ILLEGAL_INSTRUCTIONS
uint64_t inst = 0;
switch (ilc & 3) {
case 1:
- inst = ld_code2(s->pc);
+ inst = ld_code2(env, s->pc);
break;
case 2:
- inst = ld_code4(s->pc);
+ inst = ld_code4(env, s->pc);
break;
case 3:
- inst = ld_code6(s->pc);
+ inst = ld_code6(env, s->pc);
break;
}
#endif
}
-static void gen_program_exception(DisasContext *s, int ilc, int code)
+static void gen_program_exception(CPUS390XState *env, DisasContext *s, int ilc,
+ int code)
{
TCGv_i32 tmp;
- debug_print_inst(s, ilc);
+ debug_print_inst(env, s, ilc);
/* remember what pgm exeption this was */
tmp = tcg_const_i32(code);
/* trigger exception */
tmp = tcg_const_i32(EXCP_PGM);
- gen_helper_exception(tmp);
+ gen_helper_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
/* end TB here */
}
-static void gen_illegal_opcode(DisasContext *s, int ilc)
+static void gen_illegal_opcode(CPUS390XState *env, DisasContext *s, int ilc)
{
- gen_program_exception(s, ilc, PGM_SPECIFICATION);
+ gen_program_exception(env, s, ilc, PGM_SPECIFICATION);
}
-static void gen_privileged_exception(DisasContext *s, int ilc)
+static void gen_privileged_exception(CPUS390XState *env, DisasContext *s,
+ int ilc)
{
- gen_program_exception(s, ilc, PGM_PRIVILEGED);
+ gen_program_exception(env, s, ilc, PGM_PRIVILEGED);
}
-static void check_privileged(DisasContext *s, int ilc)
+static void check_privileged(CPUS390XState *env, DisasContext *s, int ilc)
{
if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
- gen_privileged_exception(s, ilc);
+ gen_privileged_exception(env, s, ilc);
}
}
s->cc_op = CC_OP_LTGT_F32;
}
-static void set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
+static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
{
gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1);
}
-static inline void set_cc_nz_f64(DisasContext *s, TCGv_i64 v1)
-{
- gen_op_update1_cc_i64(s, CC_OP_NZ_F64, v1);
-}
-
/* CC value is in env->cc_op */
static inline void set_cc_static(DisasContext *s)
{
case CC_OP_NZ_F32:
case CC_OP_NZ_F64:
/* 1 argument */
- gen_helper_calc_cc(cc_op, local_cc_op, dummy, cc_dst, dummy);
+ gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
break;
case CC_OP_ICM:
case CC_OP_LTGT_32:
case CC_OP_LTGT_F64:
case CC_OP_SLAG:
/* 2 arguments */
- gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, dummy);
+ gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
break;
case CC_OP_ADD_64:
case CC_OP_ADDU_64:
case CC_OP_SUB_32:
case CC_OP_SUBU_32:
/* 3 arguments */
- gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, cc_vr);
+ gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
break;
case CC_OP_DYNAMIC:
/* unknown operation - assume 3 arguments and cc_op in env */
- gen_helper_calc_cc(cc_op, cc_op, cc_src, cc_dst, cc_vr);
+ gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
break;
default:
tcg_abort();
/* Fall back to helper */
vl = tcg_const_i32(l);
potential_page_fault(s);
- gen_helper_mvc(vl, s1, s2);
+ gen_helper_mvc(cpu_env, vl, s1, s2);
tcg_temp_free_i32(vl);
return;
}
potential_page_fault(s);
vl = tcg_const_i32(l);
- gen_helper_clc(cc_op, vl, s1, s2);
+ gen_helper_clc(cc_op, cpu_env, vl, s1, s2);
tcg_temp_free_i32(vl);
set_cc_static(s);
}
-static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)
+static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1,
+ int x2, int b2, int d2)
{
TCGv_i64 addr, tmp, tmp2, tmp3, tmp4;
TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_const_i32(r1);
tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
- gen_helper_mlg(tmp32_1, tmp2);
+ gen_helper_mlg(cpu_env, tmp32_1, tmp2);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
break;
tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_const_i32(r1);
tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
- gen_helper_dlg(tmp32_1, tmp2);
+ gen_helper_dlg(cpu_env, tmp32_1, tmp2);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
break;
tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
/* XXX possible optimization point */
gen_op_calc_cc(s);
- gen_helper_slbg(cc_op, cc_op, tmp32_1, regs[r1], tmp2);
+ gen_helper_slbg(cc_op, cpu_env, cc_op, tmp32_1, regs[r1], tmp2);
set_cc_static(s);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
/* XXX possible optimization point */
gen_op_calc_cc(s);
- gen_helper_slb(cc_op, cc_op, tmp32_1, tmp32_2);
+ gen_helper_slb(cc_op, cpu_env, cc_op, tmp32_1, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
break;
default:
LOG_DISAS("illegal e3 operation 0x%x\n", op);
- gen_illegal_opcode(s, 3);
+ gen_illegal_opcode(env, s, 3);
break;
}
tcg_temp_free_i64(addr);
}
#ifndef CONFIG_USER_ONLY
-static void disas_e5(DisasContext* s, uint64_t insn)
+static void disas_e5(CPUS390XState *env, DisasContext* s, uint64_t insn)
{
TCGv_i64 tmp, tmp2;
int op = (insn >> 32) & 0xff;
break;
default:
LOG_DISAS("illegal e5 operation 0x%x\n", op);
- gen_illegal_opcode(s, 3);
+ gen_illegal_opcode(env, s, 3);
break;
}
}
#endif
-static void disas_eb(DisasContext *s, int op, int r1, int r3, int b2, int d2)
+static void disas_eb(CPUS390XState *env, DisasContext *s, int op, int r1,
+ int r3, int b2, int d2)
{
TCGv_i64 tmp, tmp2, tmp3, tmp4;
TCGv_i32 tmp32_1, tmp32_2;
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_stcmh(tmp32_1, tmp, tmp32_2);
+ gen_helper_stcmh(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
#ifndef CONFIG_USER_ONLY
case 0x2f: /* LCTLG R1,R3,D2(B2) [RSE] */
/* Load Control */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_lctlg(tmp32_1, tmp, tmp32_2);
+ gen_helper_lctlg(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0x25: /* STCTG R1,R3,D2(B2) [RSE] */
/* Store Control */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_stctg(tmp32_1, tmp, tmp32_2);
+ gen_helper_stctg(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
/* XXX rewrite in tcg */
- gen_helper_csg(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_csg(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
/* XXX rewrite in tcg */
- gen_helper_cdsg(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_cdsg(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
/* XXX split CC calculation out */
- gen_helper_icmh(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_icmh(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
break;
default:
LOG_DISAS("illegal eb operation 0x%x\n", op);
- gen_illegal_opcode(s, ilc);
+ gen_illegal_opcode(env, s, ilc);
break;
}
}
-static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
- int r1b)
+static void disas_ed(CPUS390XState *env, DisasContext *s, int op, int r1,
+ int x2, int b2, int d2, int r1b)
{
TCGv_i32 tmp_r1, tmp32;
TCGv_i64 addr, tmp;
switch (op) {
case 0x4: /* LDEB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_ldeb(tmp_r1, addr);
+ gen_helper_ldeb(cpu_env, tmp_r1, addr);
break;
case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_lxdb(tmp_r1, addr);
+ gen_helper_lxdb(cpu_env, tmp_r1, addr);
break;
case 0x9: /* CEB R1,D2(X2,B2) [RXE] */
tmp = tcg_temp_new_i64();
tmp32 = tcg_temp_new_i32();
tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
tcg_gen_trunc_i64_i32(tmp32, tmp);
- gen_helper_aeb(tmp_r1, tmp32);
+ gen_helper_aeb(cpu_env, tmp_r1, tmp32);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32);
tmp32 = load_freg32(r1);
- set_cc_nz_f32(s, tmp32);
+ gen_set_cc_nz_f32(s, tmp32);
tcg_temp_free_i32(tmp32);
break;
case 0xb: /* SEB R1,D2(X2,B2) [RXE] */
tmp32 = tcg_temp_new_i32();
tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
tcg_gen_trunc_i64_i32(tmp32, tmp);
- gen_helper_seb(tmp_r1, tmp32);
+ gen_helper_seb(cpu_env, tmp_r1, tmp32);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32);
tmp32 = load_freg32(r1);
- set_cc_nz_f32(s, tmp32);
+ gen_set_cc_nz_f32(s, tmp32);
tcg_temp_free_i32(tmp32);
break;
case 0xd: /* DEB R1,D2(X2,B2) [RXE] */
tmp32 = tcg_temp_new_i32();
tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
tcg_gen_trunc_i64_i32(tmp32, tmp);
- gen_helper_deb(tmp_r1, tmp32);
+ gen_helper_deb(cpu_env, tmp_r1, tmp32);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32);
break;
case 0x10: /* TCEB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_tceb(cc_op, tmp_r1, addr);
+ gen_helper_tceb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x11: /* TCDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_tcdb(cc_op, tmp_r1, addr);
+ gen_helper_tcdb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x12: /* TCXB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_tcxb(cc_op, tmp_r1, addr);
+ gen_helper_tcxb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x17: /* MEEB R1,D2(X2,B2) [RXE] */
tmp32 = tcg_temp_new_i32();
tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
tcg_gen_trunc_i64_i32(tmp32, tmp);
- gen_helper_meeb(tmp_r1, tmp32);
+ gen_helper_meeb(cpu_env, tmp_r1, tmp32);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32);
break;
case 0x19: /* CDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_cdb(cc_op, tmp_r1, addr);
+ gen_helper_cdb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x1a: /* ADB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_adb(cc_op, tmp_r1, addr);
+ gen_helper_adb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x1b: /* SDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_sdb(cc_op, tmp_r1, addr);
+ gen_helper_sdb(cc_op, cpu_env, tmp_r1, addr);
set_cc_static(s);
break;
case 0x1c: /* MDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_mdb(tmp_r1, addr);
+ gen_helper_mdb(cpu_env, tmp_r1, addr);
break;
case 0x1d: /* DDB R1,D2(X2,B2) [RXE] */
potential_page_fault(s);
- gen_helper_ddb(tmp_r1, addr);
+ gen_helper_ddb(cpu_env, tmp_r1, addr);
break;
case 0x1e: /* MADB R1,R3,D2(X2,B2) [RXF] */
/* for RXF insns, r1 is R3 and r1b is R1 */
tmp32 = tcg_const_i32(r1b);
potential_page_fault(s);
- gen_helper_madb(tmp32, addr, tmp_r1);
+ gen_helper_madb(cpu_env, tmp32, addr, tmp_r1);
tcg_temp_free_i32(tmp32);
break;
default:
LOG_DISAS("illegal ed operation 0x%x\n", op);
- gen_illegal_opcode(s, 3);
+ gen_illegal_opcode(env, s, 3);
return;
}
tcg_temp_free_i32(tmp_r1);
tcg_temp_free_i64(addr);
}
-static void disas_a5(DisasContext *s, int op, int r1, int i2)
+static void disas_a5(CPUS390XState *env, DisasContext *s, int op, int r1,
+ int i2)
{
TCGv_i64 tmp, tmp2;
TCGv_i32 tmp32;
break;
default:
LOG_DISAS("illegal a5 operation 0x%x\n", op);
- gen_illegal_opcode(s, 2);
+ gen_illegal_opcode(env, s, 2);
return;
}
}
-static void disas_a7(DisasContext *s, int op, int r1, int i2)
+static void disas_a7(CPUS390XState *env, DisasContext *s, int op, int r1,
+ int i2)
{
TCGv_i64 tmp, tmp2;
TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
break;
default:
LOG_DISAS("illegal a7 operation 0x%x\n", op);
- gen_illegal_opcode(s, 2);
+ gen_illegal_opcode(env, s, 2);
return;
}
}
-static void disas_b2(DisasContext *s, int op, uint32_t insn)
+static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
+ uint32_t insn)
{
TCGv_i64 tmp, tmp2, tmp3;
TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
case 0x22: /* IPM R1 [RRE] */
tmp32_1 = tcg_const_i32(r1);
gen_op_calc_cc(s);
- gen_helper_ipm(cc_op, tmp32_1);
+ gen_helper_ipm(cpu_env, cc_op, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x41: /* CKSM R1,R2 [RRE] */
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
potential_page_fault(s);
- gen_helper_cksm(tmp32_1, tmp32_2);
+ gen_helper_cksm(cpu_env, tmp32_1, tmp32_2);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
gen_op_movi_cc(s, 0);
tmp2 = load_reg(r1);
tmp3 = load_reg(r2);
potential_page_fault(s);
- gen_helper_mvpg(tmp, tmp2, tmp3);
+ gen_helper_mvpg(cpu_env, tmp, tmp2, tmp3);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i64(tmp3);
tmp32_2 = tcg_const_i32(r1);
tmp32_3 = tcg_const_i32(r2);
potential_page_fault(s);
- gen_helper_mvst(tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_mvst(cpu_env, tmp32_1, tmp32_2, tmp32_3);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
tcg_temp_free_i32(tmp32_3);
tmp32_2 = tcg_const_i32(r1);
tmp32_3 = tcg_const_i32(r2);
potential_page_fault(s);
- gen_helper_clst(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_clst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
tmp32_2 = tcg_const_i32(r1);
tmp32_3 = tcg_const_i32(r2);
potential_page_fault(s);
- gen_helper_srst(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_srst(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
#ifndef CONFIG_USER_ONLY
case 0x02: /* STIDP D2(B2) [S] */
/* Store CPU ID */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_stidp(tmp);
+ gen_helper_stidp(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x04: /* SCK D2(B2) [S] */
/* Set Clock */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_stck(cc_op, tmp);
+ gen_helper_stck(cc_op, cpu_env, tmp);
set_cc_static(s);
tcg_temp_free_i64(tmp);
break;
case 0x06: /* SCKC D2(B2) [S] */
/* Set Clock Comparator */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_sckc(tmp);
+ gen_helper_sckc(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x07: /* STCKC D2(B2) [S] */
/* Store Clock Comparator */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_stckc(tmp);
+ gen_helper_stckc(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x08: /* SPT D2(B2) [S] */
/* Set CPU Timer */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_spt(tmp);
+ gen_helper_spt(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x09: /* STPT D2(B2) [S] */
/* Store CPU Timer */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_stpt(tmp);
+ gen_helper_stpt(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x0a: /* SPKA D2(B2) [S] */
/* Set PSW Key from Address */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp2 = tcg_temp_new_i64();
break;
case 0x0d: /* PTLB [S] */
/* Purge TLB */
- check_privileged(s, ilc);
- gen_helper_ptlb();
+ check_privileged(env, s, ilc);
+ gen_helper_ptlb(cpu_env);
break;
case 0x10: /* SPX D2(B2) [S] */
/* Set Prefix Register */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_spx(tmp);
+ gen_helper_spx(cpu_env, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x11: /* STPX D2(B2) [S] */
/* Store Prefix */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp2 = tcg_temp_new_i64();
break;
case 0x12: /* STAP D2(B2) [S] */
/* Store CPU Address */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp2 = tcg_temp_new_i64();
break;
case 0x21: /* IPTE R1,R2 [RRE] */
/* Invalidate PTE */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
r1 = (insn >> 4) & 0xf;
r2 = insn & 0xf;
tmp = load_reg(r1);
tmp2 = load_reg(r2);
- gen_helper_ipte(tmp, tmp2);
+ gen_helper_ipte(cpu_env, tmp, tmp2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
break;
case 0x29: /* ISKE R1,R2 [RRE] */
/* Insert Storage Key Extended */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
r1 = (insn >> 4) & 0xf;
r2 = insn & 0xf;
tmp = load_reg(r2);
tmp2 = tcg_temp_new_i64();
- gen_helper_iske(tmp2, tmp);
+ gen_helper_iske(tmp2, cpu_env, tmp);
store_reg(r1, tmp2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
break;
case 0x2a: /* RRBE R1,R2 [RRE] */
/* Set Storage Key Extended */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
r1 = (insn >> 4) & 0xf;
r2 = insn & 0xf;
tmp32_1 = load_reg32(r1);
tmp = load_reg(r2);
- gen_helper_rrbe(cc_op, tmp32_1, tmp);
+ gen_helper_rrbe(cc_op, cpu_env, tmp32_1, tmp);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp);
break;
case 0x2b: /* SSKE R1,R2 [RRE] */
/* Set Storage Key Extended */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
r1 = (insn >> 4) & 0xf;
r2 = insn & 0xf;
tmp32_1 = load_reg32(r1);
tmp = load_reg(r2);
- gen_helper_sske(tmp32_1, tmp);
+ gen_helper_sske(cpu_env, tmp32_1, tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp);
break;
case 0x34: /* STCH ? */
/* Store Subchannel */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
gen_op_movi_cc(s, 3);
break;
case 0x46: /* STURA R1,R2 [RRE] */
/* Store Using Real Address */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
r1 = (insn >> 4) & 0xf;
r2 = insn & 0xf;
tmp32_1 = load_reg32(r1);
tmp = load_reg(r2);
potential_page_fault(s);
- gen_helper_stura(tmp, tmp32_1);
+ gen_helper_stura(cpu_env, tmp, tmp32_1);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp);
break;
case 0x50: /* CSP R1,R2 [RRE] */
/* Compare And Swap And Purge */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
r1 = (insn >> 4) & 0xf;
r2 = insn & 0xf;
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
- gen_helper_csp(cc_op, tmp32_1, tmp32_2);
+ gen_helper_csp(cc_op, cpu_env, tmp32_1, tmp32_2);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0x5f: /* CHSC ? */
/* Channel Subsystem Call */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
gen_op_movi_cc(s, 3);
break;
case 0x78: /* STCKE D2(B2) [S] */
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_stcke(cc_op, tmp);
+ gen_helper_stcke(cc_op, cpu_env, tmp);
set_cc_static(s);
tcg_temp_free_i64(tmp);
break;
case 0x79: /* SACF D2(B2) [S] */
/* Store Clock Extended */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
potential_page_fault(s);
- gen_helper_sacf(tmp);
+ gen_helper_sacf(cpu_env, tmp);
tcg_temp_free_i64(tmp);
/* addressing mode has changed, so end the block */
s->pc += ilc * 2;
s->is_jmp = DISAS_EXCP;
break;
case 0x7d: /* STSI D2,(B2) [S] */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = load_reg32(0);
tmp32_2 = load_reg32(1);
potential_page_fault(s);
- gen_helper_stsi(cc_op, tmp, tmp32_1, tmp32_2);
+ gen_helper_stsi(cc_op, cpu_env, tmp, tmp32_1, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
break;
case 0xb1: /* STFL D2(B2) [S] */
/* Store Facility List (CPU features) at 200 */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
tmp2 = tcg_const_i64(0xc0000000);
tmp = tcg_const_i64(200);
tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
break;
case 0xb2: /* LPSWE D2(B2) [S] */
/* Load PSW Extended */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp2 = tcg_temp_new_i64();
tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
tcg_gen_addi_i64(tmp, tmp, 8);
tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
- gen_helper_load_psw(tmp2, tmp3);
+ gen_helper_load_psw(cpu_env, tmp2, tmp3);
/* we need to keep cc_op intact */
s->is_jmp = DISAS_JUMP;
tcg_temp_free_i64(tmp);
break;
case 0x20: /* SERVC R1,R2 [RRE] */
/* SCLP Service call (PV hypercall) */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
potential_page_fault(s);
tmp32_1 = load_reg32(r2);
tmp = load_reg(r1);
- gen_helper_servc(cc_op, tmp32_1, tmp);
+ gen_helper_servc(cc_op, cpu_env, tmp32_1, tmp);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp);
#endif
default:
LOG_DISAS("illegal b2 operation 0x%x\n", op);
- gen_illegal_opcode(s, ilc);
+ gen_illegal_opcode(env, s, ilc);
break;
}
}
-static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
+static void disas_b3(CPUS390XState *env, DisasContext *s, int op, int m3,
+ int r1, int r2)
{
TCGv_i64 tmp;
TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
#define FP_HELPER(i) \
tmp32_1 = tcg_const_i32(r1); \
tmp32_2 = tcg_const_i32(r2); \
- gen_helper_ ## i (tmp32_1, tmp32_2); \
+ gen_helper_ ## i(cpu_env, tmp32_1, tmp32_2); \
tcg_temp_free_i32(tmp32_1); \
tcg_temp_free_i32(tmp32_2);
#define FP_HELPER_CC(i) \
tmp32_1 = tcg_const_i32(r1); \
tmp32_2 = tcg_const_i32(r2); \
- gen_helper_ ## i (cc_op, tmp32_1, tmp32_2); \
+ gen_helper_ ## i(cc_op, cpu_env, tmp32_1, tmp32_2); \
set_cc_static(s); \
tcg_temp_free_i32(tmp32_1); \
tcg_temp_free_i32(tmp32_2);
tmp32_3 = tcg_const_i32(r1);
switch (op) {
case 0xe:
- gen_helper_maebr(tmp32_1, tmp32_3, tmp32_2);
+ gen_helper_maebr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
break;
case 0x1e:
- gen_helper_madbr(tmp32_1, tmp32_3, tmp32_2);
+ gen_helper_madbr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
break;
case 0x1f:
- gen_helper_msdbr(tmp32_1, tmp32_3, tmp32_2);
+ gen_helper_msdbr(cpu_env, tmp32_1, tmp32_3, tmp32_2);
break;
default:
tcg_abort();
break;
case 0x74: /* LZER R1 [RRE] */
tmp32_1 = tcg_const_i32(r1);
- gen_helper_lzer(tmp32_1);
+ gen_helper_lzer(cpu_env, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x75: /* LZDR R1 [RRE] */
tmp32_1 = tcg_const_i32(r1);
- gen_helper_lzdr(tmp32_1);
+ gen_helper_lzdr(cpu_env, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x76: /* LZXR R1 [RRE] */
tmp32_1 = tcg_const_i32(r1);
- gen_helper_lzxr(tmp32_1);
+ gen_helper_lzxr(cpu_env, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x84: /* SFPC R1 [RRE] */
tmp32_2 = load_reg32(r2);
switch (op) {
case 0x94:
- gen_helper_cefbr(tmp32_1, tmp32_2);
+ gen_helper_cefbr(cpu_env, tmp32_1, tmp32_2);
break;
case 0x95:
- gen_helper_cdfbr(tmp32_1, tmp32_2);
+ gen_helper_cdfbr(cpu_env, tmp32_1, tmp32_2);
break;
case 0x96:
- gen_helper_cxfbr(tmp32_1, tmp32_2);
+ gen_helper_cxfbr(cpu_env, tmp32_1, tmp32_2);
break;
default:
tcg_abort();
tmp32_3 = tcg_const_i32(m3);
switch (op) {
case 0x98:
- gen_helper_cfebr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cfebr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
break;
case 0x99:
- gen_helper_cfdbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cfdbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
break;
case 0x9a:
- gen_helper_cfxbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cfxbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
break;
default:
tcg_abort();
tmp = load_reg(r2);
switch (op) {
case 0xa4:
- gen_helper_cegbr(tmp32_1, tmp);
+ gen_helper_cegbr(cpu_env, tmp32_1, tmp);
break;
case 0xa5:
- gen_helper_cdgbr(tmp32_1, tmp);
+ gen_helper_cdgbr(cpu_env, tmp32_1, tmp);
break;
default:
tcg_abort();
case 0xa6: /* CXGBR R1,R2 [RRE] */
tmp32_1 = tcg_const_i32(r1);
tmp = load_reg(r2);
- gen_helper_cxgbr(tmp32_1, tmp);
+ gen_helper_cxgbr(cpu_env, tmp32_1, tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp);
break;
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
tmp32_3 = tcg_const_i32(m3);
- gen_helper_cgebr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cgebr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
tmp32_3 = tcg_const_i32(m3);
- gen_helper_cgdbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cgdbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
tmp32_3 = tcg_const_i32(m3);
- gen_helper_cgxbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
+ gen_helper_cgxbr(cc_op, cpu_env, tmp32_1, tmp32_2, tmp32_3);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
default:
LOG_DISAS("illegal b3 operation 0x%x\n", op);
- gen_illegal_opcode(s, 2);
+ gen_illegal_opcode(env, s, 2);
break;
}
#undef FP_HELPER
}
-static void disas_b9(DisasContext *s, int op, int r1, int r2)
+static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,
+ int r2)
{
TCGv_i64 tmp, tmp2, tmp3;
TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
case 0x83: /* FLOGR R1,R2 [RRE] */
tmp = load_reg(r2);
tmp32_1 = tcg_const_i32(r1);
- gen_helper_flogr(cc_op, tmp32_1, tmp);
+ gen_helper_flogr(cc_op, cpu_env, tmp32_1, tmp);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
case 0x87: /* DLGR R1,R2 [RRE] */
tmp32_1 = tcg_const_i32(r1);
tmp = load_reg(r2);
- gen_helper_dlg(tmp32_1, tmp);
+ gen_helper_dlg(cpu_env, tmp32_1, tmp);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
break;
tmp2 = load_reg(r2);
tmp32_1 = tcg_const_i32(r1);
gen_op_calc_cc(s);
- gen_helper_slbg(cc_op, cc_op, tmp32_1, tmp, tmp2);
+ gen_helper_slbg(cc_op, cpu_env, cc_op, tmp32_1, tmp, tmp2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
tmp32_1 = load_reg32(r2);
tmp32_2 = tcg_const_i32(r1);
gen_op_calc_cc(s);
- gen_helper_slb(cc_op, cc_op, tmp32_2, tmp32_1);
+ gen_helper_slb(cc_op, cpu_env, cc_op, tmp32_2, tmp32_1);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
default:
LOG_DISAS("illegal b9 operation 0x%x\n", op);
- gen_illegal_opcode(s, 2);
+ gen_illegal_opcode(env, s, 2);
break;
}
}
-static void disas_c0(DisasContext *s, int op, int r1, int i2)
+static void disas_c0(CPUS390XState *env, DisasContext *s, int op, int r1, int i2)
{
TCGv_i64 tmp;
TCGv_i32 tmp32_1, tmp32_2;
break;
default:
LOG_DISAS("illegal c0 operation 0x%x\n", op);
- gen_illegal_opcode(s, 3);
+ gen_illegal_opcode(env, s, 3);
break;
}
}
-static void disas_c2(DisasContext *s, int op, int r1, int i2)
+static void disas_c2(CPUS390XState *env, DisasContext *s, int op, int r1,
+ int i2)
{
TCGv_i64 tmp, tmp2, tmp3;
TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
break;
default:
LOG_DISAS("illegal c2 operation 0x%x\n", op);
- gen_illegal_opcode(s, 3);
+ gen_illegal_opcode(env, s, 3);
break;
}
}
}
}
-static void disas_s390_insn(DisasContext *s)
+static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
{
TCGv_i64 tmp, tmp2, tmp3, tmp4;
TCGv_i32 tmp32_1, tmp32_2, tmp32_3, tmp32_4;
int ilc;
int l1;
- opc = ldub_code(s->pc);
+ opc = cpu_ldub_code(env, s->pc);
LOG_DISAS("opc 0x%x\n", opc);
ilc = get_ilc(opc);
switch (opc) {
#ifndef CONFIG_USER_ONLY
case 0x01: /* SAM */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
/* set addressing mode, but we only do 64bit anyways */
break;
#endif
case 0x6: /* BCTR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_reg32(r1);
tcg_gen_subi_i32(tmp32_1, tmp32_1, 1);
}
break;
case 0x7: /* BCR M1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
if (r2) {
tmp = load_reg(r2);
}
break;
case 0xa: /* SVC I [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
debug_insn(insn);
i = insn & 0xff;
update_psw_addr(s);
tmp32_3 = tcg_const_i32(EXCP_SVC);
tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, int_svc_code));
tcg_gen_st_i32(tmp32_2, cpu_env, offsetof(CPUS390XState, int_svc_ilc));
- gen_helper_exception(tmp32_3);
+ gen_helper_exception(cpu_env, tmp32_3);
s->is_jmp = DISAS_EXCP;
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
tcg_temp_free_i32(tmp32_3);
break;
case 0xd: /* BASR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 2));
store_reg(r1, tmp);
tcg_temp_free_i64(tmp);
break;
case 0xe: /* MVCL R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
potential_page_fault(s);
- gen_helper_mvcl(cc_op, tmp32_1, tmp32_2);
+ gen_helper_mvcl(cc_op, cpu_env, tmp32_1, tmp32_2);
set_cc_static(s);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0x10: /* LPR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_reg32(r2);
set_cc_abs32(s, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x11: /* LNR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_reg32(r2);
set_cc_nabs32(s, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x12: /* LTR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_reg32(r2);
if (r1 != r2) {
tcg_temp_free_i32(tmp32_1);
break;
case 0x13: /* LCR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_reg32(r2);
tcg_gen_neg_i32(tmp32_1, tmp32_1);
case 0x14: /* NR R1,R2 [RR] */
case 0x16: /* OR R1,R2 [RR] */
case 0x17: /* XR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_2 = load_reg32(r2);
tmp32_1 = load_reg32(r1);
tcg_temp_free_i32(tmp32_2);
break;
case 0x18: /* LR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_reg32(r2);
store_reg32(r1, tmp32_1);
break;
case 0x15: /* CLR R1,R2 [RR] */
case 0x19: /* CR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_reg32(r1);
tmp32_2 = load_reg32(r2);
break;
case 0x1a: /* AR R1,R2 [RR] */
case 0x1e: /* ALR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_reg32(r1);
tmp32_2 = load_reg32(r2);
break;
case 0x1b: /* SR R1,R2 [RR] */
case 0x1f: /* SLR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_reg32(r1);
tmp32_2 = load_reg32(r2);
break;
case 0x1c: /* MR R1,R2 [RR] */
/* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp2 = load_reg(r2);
tmp3 = load_reg((r1 + 1) & 15);
tcg_temp_free_i64(tmp3);
break;
case 0x1d: /* DR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_reg32(r1);
tmp32_2 = load_reg32(r1 + 1);
tcg_temp_free_i64(tmp3);
break;
case 0x28: /* LDR R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp = load_freg(r2);
store_freg(r1, tmp);
tcg_temp_free_i64(tmp);
break;
case 0x38: /* LER R1,R2 [RR] */
- insn = ld_code2(s->pc);
+ insn = ld_code2(env, s->pc);
decode_rr(s, insn, &r1, &r2);
tmp32_1 = load_freg32(r2);
store_freg32(r1, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x40: /* STH R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = load_reg(r1);
tcg_gen_qemu_st16(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp2);
break;
case 0x41: /* la */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
store_reg(r1, tmp); /* FIXME: 31/24-bit addressing */
tcg_temp_free_i64(tmp);
break;
case 0x42: /* STC R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = load_reg(r1);
tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp2);
break;
case 0x43: /* IC R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp2);
break;
case 0x44: /* EX R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = load_reg(r1);
tmp3 = tcg_const_i64(s->pc + 4);
update_psw_addr(s);
gen_op_calc_cc(s);
- gen_helper_ex(cc_op, cc_op, tmp2, tmp, tmp3);
+ gen_helper_ex(cc_op, cpu_env, cc_op, tmp2, tmp, tmp3);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i64(tmp3);
break;
case 0x46: /* BCT R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp);
break;
case 0x47: /* BC M1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
gen_bcr(s, r1, tmp, s->pc + 4);
tcg_temp_free_i64(tmp);
s->is_jmp = DISAS_TB_JUMP;
break;
case 0x48: /* LH R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp2);
break;
case 0x49: /* CH R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp32_1 = load_reg32(r1);
tmp32_2 = tcg_temp_new_i32();
case 0x4a: /* AH R1,D2(X2,B2) [RX] */
case 0x4b: /* SH R1,D2(X2,B2) [RX] */
case 0x4c: /* MH R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tmp32_1 = load_reg32(r1);
tcg_temp_free_i64(tmp2);
break;
case 0x4d: /* BAS R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_const_i64(pc_to_link_info(s, s->pc + 4));
store_reg(r1, tmp2);
s->is_jmp = DISAS_JUMP;
break;
case 0x4e: /* CVD R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_temp_new_i32();
tcg_temp_free_i32(tmp32_1);
break;
case 0x50: /* st r1, d2(x2, b2) */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = load_reg(r1);
tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp2);
break;
case 0x55: /* CL R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_temp_new_i32();
case 0x54: /* N R1,D2(X2,B2) [RX] */
case 0x56: /* O R1,D2(X2,B2) [RX] */
case 0x57: /* X R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tmp32_1 = load_reg32(r1);
tcg_temp_free_i32(tmp32_2);
break;
case 0x58: /* l r1, d2(x2, b2) */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_temp_new_i32();
tcg_temp_free_i32(tmp32_1);
break;
case 0x59: /* C R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_temp_new_i32();
case 0x5b: /* S R1,D2(X2,B2) [RX] */
case 0x5e: /* AL R1,D2(X2,B2) [RX] */
case 0x5f: /* SL R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp32_1 = load_reg32(r1);
tmp32_2 = tcg_temp_new_i32();
break;
case 0x5c: /* M R1,D2(X2,B2) [RX] */
/* reg(r1, r1+1) = reg(r1+1) * *(s32*)addr */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp3);
break;
case 0x5d: /* D R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp3 = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp32_1 = load_reg32(r1);
tmp32_2 = load_reg32(r1 + 1);
tcg_temp_free_i64(tmp3);
break;
case 0x60: /* STD R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = load_freg(r1);
tcg_gen_qemu_st64(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp2);
break;
case 0x68: /* LD R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp2);
break;
case 0x70: /* STE R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tmp32_1 = load_freg32(r1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x71: /* MS R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tmp32_1 = load_reg32(r1);
tcg_temp_free_i32(tmp32_2);
break;
case 0x78: /* LE R1,D2(X2,B2) [RX] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp2 = tcg_temp_new_i64();
tmp32_1 = tcg_temp_new_i32();
#ifndef CONFIG_USER_ONLY
case 0x80: /* SSM D2(B2) [S] */
/* Set System Mask */
- check_privileged(s, ilc);
- insn = ld_code4(s->pc);
+ check_privileged(env, s, ilc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp2 = tcg_temp_new_i64();
break;
case 0x82: /* LPSW D2(B2) [S] */
/* Load PSW */
- check_privileged(s, ilc);
- insn = ld_code4(s->pc);
+ check_privileged(env, s, ilc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp2 = tcg_temp_new_i64();
tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
tcg_gen_addi_i64(tmp, tmp, 4);
tcg_gen_qemu_ld32u(tmp3, tmp, get_mem_index(s));
- gen_helper_load_psw(tmp2, tmp3);
+ gen_helper_load_psw(cpu_env, tmp2, tmp3);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i64(tmp3);
break;
case 0x83: /* DIAG R1,R3,D2 [RS] */
/* Diagnose call (KVM hypercall) */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
potential_page_fault(s);
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp32_1 = tcg_const_i32(insn & 0xfff);
tmp2 = load_reg(2);
tmp3 = load_reg(1);
- gen_helper_diag(tmp2, tmp32_1, tmp2, tmp3);
+ gen_helper_diag(tmp2, cpu_env, tmp32_1, tmp2, tmp3);
store_reg(2, tmp2);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i64(tmp2);
case 0x88: /* SRL R1,D2(B2) [RS] */
case 0x89: /* SLL R1,D2(B2) [RS] */
case 0x8a: /* SRA R1,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = load_reg32(r1);
case 0x8c: /* SRDL R1,D2(B2) [RS] */
case 0x8d: /* SLDL R1,D2(B2) [RS] */
case 0x8e: /* SRDA R1,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2); /* shift */
tmp2 = tcg_temp_new_i64();
break;
case 0x98: /* LM R1,R3,D2(B2) [RS] */
case 0x90: /* STM R1,R3,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tcg_temp_free_i64(tmp4);
break;
case 0x91: /* TM D1(B1),I2 [SI] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_si(s, insn, &i2, &b1, &d1);
tmp2 = tcg_const_i64(i2);
tcg_gen_qemu_ld8u(tmp, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp2);
break;
case 0x92: /* MVI D1(B1),I2 [SI] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_si(s, insn, &i2, &b1, &d1);
tmp2 = tcg_const_i64(i2);
tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
case 0x94: /* NI D1(B1),I2 [SI] */
case 0x96: /* OI D1(B1),I2 [SI] */
case 0x97: /* XI D1(B1),I2 [SI] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_si(s, insn, &i2, &b1, &d1);
tmp2 = tcg_temp_new_i64();
tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp2);
break;
case 0x95: /* CLI D1(B1),I2 [SI] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
tmp = decode_si(s, insn, &i2, &b1, &d1);
tmp2 = tcg_temp_new_i64();
tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
tcg_temp_free_i64(tmp2);
break;
case 0x9a: /* LAM R1,R3,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_lam(tmp32_1, tmp, tmp32_2);
+ gen_helper_lam(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0x9b: /* STAM R1,R3,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_stam(tmp32_1, tmp, tmp32_2);
+ gen_helper_stam(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0xa5:
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
r1 = (insn >> 20) & 0xf;
op = (insn >> 16) & 0xf;
i2 = insn & 0xffff;
- disas_a5(s, op, r1, i2);
+ disas_a5(env, s, op, r1, i2);
break;
case 0xa7:
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
r1 = (insn >> 20) & 0xf;
op = (insn >> 16) & 0xf;
i2 = (short)insn;
- disas_a7(s, op, r1, i2);
+ disas_a7(env, s, op, r1, i2);
break;
case 0xa8: /* MVCLE R1,R3,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_mvcle(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_mvcle(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0xa9: /* CLCLE R1,R3,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_clcle(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_clcle(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
#ifndef CONFIG_USER_ONLY
case 0xac: /* STNSM D1(B1),I2 [SI] */
case 0xad: /* STOSM D1(B1),I2 [SI] */
- check_privileged(s, ilc);
- insn = ld_code4(s->pc);
+ check_privileged(env, s, ilc);
+ insn = ld_code4(env, s->pc);
tmp = decode_si(s, insn, &i2, &b1, &d1);
tmp2 = tcg_temp_new_i64();
tcg_gen_shri_i64(tmp2, psw_mask, 56);
tcg_temp_free_i64(tmp2);
break;
case 0xae: /* SIGP R1,R3,D2(B2) [RS] */
- check_privileged(s, ilc);
- insn = ld_code4(s->pc);
+ check_privileged(env, s, ilc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp2 = load_reg(r3);
tmp32_1 = tcg_const_i32(r1);
potential_page_fault(s);
- gen_helper_sigp(cc_op, tmp, tmp32_1, tmp2);
+ gen_helper_sigp(cc_op, cpu_env, tmp, tmp32_1, tmp2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
tcg_temp_free_i32(tmp32_1);
break;
case 0xb1: /* LRA R1,D2(X2, B2) [RX] */
- check_privileged(s, ilc);
- insn = ld_code4(s->pc);
+ check_privileged(env, s, ilc);
+ insn = ld_code4(env, s->pc);
tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
tmp32_1 = tcg_const_i32(r1);
potential_page_fault(s);
- gen_helper_lra(cc_op, tmp, tmp32_1);
+ gen_helper_lra(cc_op, cpu_env, tmp, tmp32_1);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
break;
#endif
case 0xb2:
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
op = (insn >> 16) & 0xff;
switch (op) {
case 0x9c: /* STFPC D2(B2) [S] */
tcg_temp_free_i64(tmp2);
break;
default:
- disas_b2(s, op, insn);
+ disas_b2(env, s, op, insn);
break;
}
break;
case 0xb3:
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
op = (insn >> 16) & 0xff;
r3 = (insn >> 12) & 0xf; /* aka m3 */
r1 = (insn >> 4) & 0xf;
r2 = insn & 0xf;
- disas_b3(s, op, r3, r1, r2);
+ disas_b3(env, s, op, r3, r1, r2);
break;
#ifndef CONFIG_USER_ONLY
case 0xb6: /* STCTL R1,R3,D2(B2) [RS] */
/* Store Control */
- check_privileged(s, ilc);
- insn = ld_code4(s->pc);
+ check_privileged(env, s, ilc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_stctl(tmp32_1, tmp, tmp32_2);
+ gen_helper_stctl(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0xb7: /* LCTL R1,R3,D2(B2) [RS] */
/* Load Control */
- check_privileged(s, ilc);
- insn = ld_code4(s->pc);
+ check_privileged(env, s, ilc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_lctl(tmp32_1, tmp, tmp32_2);
+ gen_helper_lctl(cpu_env, tmp32_1, tmp, tmp32_2);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
#endif
case 0xb9:
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
r1 = (insn >> 4) & 0xf;
r2 = insn & 0xf;
op = (insn >> 16) & 0xff;
- disas_b9(s, op, r1, r2);
+ disas_b9(env, s, op, r1, r2);
break;
case 0xba: /* CS R1,R3,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_cs(cc_op, tmp32_1, tmp, tmp32_2);
+ gen_helper_cs(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0xbd: /* CLM R1,M3,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = load_reg32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_clm(cc_op, tmp32_1, tmp32_2, tmp);
+ gen_helper_clm(cc_op, cpu_env, tmp32_1, tmp32_2, tmp);
set_cc_static(s);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0xbe: /* STCM R1,M3,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
tmp = get_address(s, 0, b2, d2);
tmp32_1 = load_reg32(r1);
tmp32_2 = tcg_const_i32(r3);
potential_page_fault(s);
- gen_helper_stcm(tmp32_1, tmp32_2, tmp);
+ gen_helper_stcm(cpu_env, tmp32_1, tmp32_2, tmp);
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
break;
case 0xbf: /* ICM R1,M3,D2(B2) [RS] */
- insn = ld_code4(s->pc);
+ insn = ld_code4(env, s->pc);
decode_rs(s, insn, &r1, &r3, &b2, &d2);
if (r3 == 15) {
/* effectively a 32-bit load */
break;
case 0xc0:
case 0xc2:
- insn = ld_code6(s->pc);
+ insn = ld_code6(env, s->pc);
r1 = (insn >> 36) & 0xf;
op = (insn >> 32) & 0xf;
i2 = (int)insn;
switch (opc) {
case 0xc0:
- disas_c0(s, op, r1, i2);
+ disas_c0(env, s, op, r1, i2);
break;
case 0xc2:
- disas_c2(s, op, r1, i2);
+ disas_c2(env, s, op, r1, i2);
break;
default:
tcg_abort();
case 0xd7: /* XC D1(L,B1),D2(B2) [SS] */
case 0xdc: /* TR D1(L,B1),D2(B2) [SS] */
case 0xf3: /* UNPK D1(L1,B1),D2(L2,B2) [SS] */
- insn = ld_code6(s->pc);
+ insn = ld_code6(env, s->pc);
vl = tcg_const_i32((insn >> 32) & 0xff);
b1 = (insn >> 28) & 0xf;
b2 = (insn >> 12) & 0xf;
break;
case 0xd4:
potential_page_fault(s);
- gen_helper_nc(cc_op, vl, tmp, tmp2);
+ gen_helper_nc(cc_op, cpu_env, vl, tmp, tmp2);
set_cc_static(s);
break;
case 0xd5:
break;
case 0xd6:
potential_page_fault(s);
- gen_helper_oc(cc_op, vl, tmp, tmp2);
+ gen_helper_oc(cc_op, cpu_env, vl, tmp, tmp2);
set_cc_static(s);
break;
case 0xd7:
potential_page_fault(s);
- gen_helper_xc(cc_op, vl, tmp, tmp2);
+ gen_helper_xc(cc_op, cpu_env, vl, tmp, tmp2);
set_cc_static(s);
break;
case 0xdc:
potential_page_fault(s);
- gen_helper_tr(vl, tmp, tmp2);
+ gen_helper_tr(cpu_env, vl, tmp, tmp2);
set_cc_static(s);
break;
case 0xf3:
potential_page_fault(s);
- gen_helper_unpk(vl, tmp, tmp2);
+ gen_helper_unpk(cpu_env, vl, tmp, tmp2);
break;
default:
tcg_abort();
#ifndef CONFIG_USER_ONLY
case 0xda: /* MVCP D1(R1,B1),D2(B2),R3 [SS] */
case 0xdb: /* MVCS D1(R1,B1),D2(B2),R3 [SS] */
- check_privileged(s, ilc);
+ check_privileged(env, s, ilc);
potential_page_fault(s);
- insn = ld_code6(s->pc);
+ insn = ld_code6(env, s->pc);
r1 = (insn >> 36) & 0xf;
r3 = (insn >> 32) & 0xf;
b1 = (insn >> 28) & 0xf;
tmp2 = get_address(s, 0, b1, d1);
tmp3 = get_address(s, 0, b2, d2);
if (opc == 0xda) {
- gen_helper_mvcp(cc_op, tmp, tmp2, tmp3);
+ gen_helper_mvcp(cc_op, cpu_env, tmp, tmp2, tmp3);
} else {
- gen_helper_mvcs(cc_op, tmp, tmp2, tmp3);
+ gen_helper_mvcs(cc_op, cpu_env, tmp, tmp2, tmp3);
}
set_cc_static(s);
tcg_temp_free_i64(tmp);
break;
#endif
case 0xe3:
- insn = ld_code6(s->pc);
+ insn = ld_code6(env, s->pc);
debug_insn(insn);
op = insn & 0xff;
r1 = (insn >> 36) & 0xf;
b2 = (insn >> 28) & 0xf;
d2 = ((int)((((insn >> 16) & 0xfff)
| ((insn << 4) & 0xff000)) << 12)) >> 12;
- disas_e3(s, op, r1, x2, b2, d2 );
+ disas_e3(env, s, op, r1, x2, b2, d2 );
break;
#ifndef CONFIG_USER_ONLY
case 0xe5:
/* Test Protection */
- check_privileged(s, ilc);
- insn = ld_code6(s->pc);
+ check_privileged(env, s, ilc);
+ insn = ld_code6(env, s->pc);
debug_insn(insn);
- disas_e5(s, insn);
+ disas_e5(env, s, insn);
break;
#endif
case 0xeb:
- insn = ld_code6(s->pc);
+ insn = ld_code6(env, s->pc);
debug_insn(insn);
op = insn & 0xff;
r1 = (insn >> 36) & 0xf;
b2 = (insn >> 28) & 0xf;
d2 = ((int)((((insn >> 16) & 0xfff)
| ((insn << 4) & 0xff000)) << 12)) >> 12;
- disas_eb(s, op, r1, r3, b2, d2);
+ disas_eb(env, s, op, r1, r3, b2, d2);
break;
case 0xed:
- insn = ld_code6(s->pc);
+ insn = ld_code6(env, s->pc);
debug_insn(insn);
op = insn & 0xff;
r1 = (insn >> 36) & 0xf;
b2 = (insn >> 28) & 0xf;
d2 = (short)((insn >> 16) & 0xfff);
r1b = (insn >> 12) & 0xf;
- disas_ed(s, op, r1, x2, b2, d2, r1b);
+ disas_ed(env, s, op, r1, x2, b2, d2, r1b);
break;
default:
qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc);
- gen_illegal_opcode(s, ilc);
+ gen_illegal_opcode(env, s, ilc);
break;
}
dc.tb = tb;
dc.cc_op = CC_OP_DYNAMIC;
- gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
+ gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
}
}
if (search_pc) {
- j = gen_opc_ptr - gen_opc_buf;
+ j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
if (lj < j) {
lj++;
while (lj < j) {
- gen_opc_instr_start[lj++] = 0;
+ tcg_ctx.gen_opc_instr_start[lj++] = 0;
}
}
- gen_opc_pc[lj] = dc.pc;
+ tcg_ctx.gen_opc_pc[lj] = dc.pc;
gen_opc_cc_op[lj] = dc.cc_op;
- gen_opc_instr_start[lj] = 1;
- gen_opc_icount[lj] = num_insns;
+ tcg_ctx.gen_opc_instr_start[lj] = 1;
+ tcg_ctx.gen_opc_icount[lj] = num_insns;
}
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}
-#if defined(S390X_DEBUG_DISAS_VERBOSE)
- LOG_DISAS("pc " TARGET_FMT_lx "\n",
- dc.pc);
-#endif
- disas_s390_insn(&dc);
+
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
+ tcg_gen_debug_insn_start(dc.pc);
+ }
+
+ disas_s390_insn(env, &dc);
num_insns++;
if (env->singlestep_enabled) {
gen_debug(&dc);
}
- } while (!dc.is_jmp && gen_opc_ptr < gen_opc_end && dc.pc < next_page_start
+ } while (!dc.is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end
+ && dc.pc < next_page_start
&& num_insns < max_insns && !env->singlestep_enabled
&& !singlestep);
tcg_gen_exit_tb(0);
}
gen_icount_end(tb, num_insns);
- *gen_opc_ptr = INDEX_op_end;
+ *tcg_ctx.gen_opc_ptr = INDEX_op_end;
if (search_pc) {
- j = gen_opc_ptr - gen_opc_buf;
+ j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
lj++;
while (lj <= j) {
- gen_opc_instr_start[lj++] = 0;
+ tcg_ctx.gen_opc_instr_start[lj++] = 0;
}
} else {
tb->size = dc.pc - pc_start;
tb->icount = num_insns;
}
#if defined(S390X_DEBUG_DISAS)
- log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(pc_start, dc.pc - pc_start, 1);
+ log_target_disas(env, pc_start, dc.pc - pc_start, 1);
qemu_log("\n");
}
#endif
void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
{
int cc_op;
- env->psw.addr = gen_opc_pc[pc_pos];
+ env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
cc_op = gen_opc_cc_op[pc_pos];
if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
env->cc_op = cc_op;
projects / mirror_qemu.git / blobdiff