#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
-
-enum {
-#define DEF(s, n, copy_size) INDEX_op_ ## s,
-#include "opc.h"
-#undef DEF
- NB_OPS,
-};
-
-#ifdef USE_DIRECT_JUMP
-#define TBPARAM(x)
-#else
-#define TBPARAM(x) ((long)(x))
-#endif
-
-static uint16_t *gen_opc_ptr;
-static uint32_t *gen_opparam_ptr;
-
-#include "gen-op.h"
+#include "tcg-op.h"
+#include "qemu-common.h"
typedef struct DisasContext {
struct TranslationBlock *tb;
uint32_t fpscr;
uint16_t opcode;
uint32_t flags;
+ int bstate;
int memidx;
uint32_t delayed_pc;
int singlestep_enabled;
} DisasContext;
+enum {
+ BS_NONE = 0, /* We go out of the TB without reaching a branch or an
+ * exception condition
+ */
+ BS_STOP = 1, /* We want to stop translation for any reason */
+ BS_BRANCH = 2, /* We reached a branch condition */
+ BS_EXCP = 3, /* We reached an exception condition */
+};
+
+static TCGv cpu_env;
+
+#include "gen-icount.h"
+
+void sh4_translate_init()
+{
+ static int done_init = 0;
+ if (done_init)
+ return;
+ cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
+ done_init = 1;
+}
+
#ifdef CONFIG_USER_ONLY
#define GEN_OP_LD(width, reg) \
if (!env)
return NULL;
cpu_exec_init(env);
+ sh4_translate_init();
cpu_sh4_reset(env);
tlb_flush(env, 1);
return env;
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
!ctx->singlestep_enabled) {
/* Use a direct jump if in same page and singlestep not enabled */
- if (n == 0)
- gen_op_goto_tb0(TBPARAM(tb));
- else
- gen_op_goto_tb1(TBPARAM(tb));
- gen_op_movl_imm_T0((long) tb + n);
+ tcg_gen_goto_tb(n);
+ gen_op_movl_imm_PC(dest);
+ tcg_gen_exit_tb((long) tb + n);
} else {
- gen_op_movl_imm_T0(0);
+ gen_op_movl_imm_PC(dest);
+ if (ctx->singlestep_enabled)
+ gen_op_debug();
+ tcg_gen_exit_tb(0);
}
- gen_op_movl_imm_PC(dest);
- if (ctx->singlestep_enabled)
- gen_op_debug();
- gen_op_exit_tb();
-}
-
-/* Jump to pc after an exception */
-static void gen_jump_exception(DisasContext * ctx)
-{
- gen_op_movl_imm_T0(0);
- if (ctx->singlestep_enabled)
- gen_op_debug();
- gen_op_exit_tb();
}
static void gen_jump(DisasContext * ctx)
/* Target is not statically known, it comes necessarily from a
delayed jump as immediate jump are conditinal jumps */
gen_op_movl_delayed_pc_PC();
- gen_op_movl_imm_T0(0);
if (ctx->singlestep_enabled)
gen_op_debug();
- gen_op_exit_tb();
+ tcg_gen_exit_tb(0);
} else {
gen_goto_tb(ctx, 0, ctx->delayed_pc);
}
l1 = gen_new_label();
gen_op_jdelayed(l1);
- gen_goto_tb(ctx, 1, ctx->pc);
+ gen_goto_tb(ctx, 1, ctx->pc + 2);
gen_set_label(l1);
gen_jump(ctx);
}
#define CHECK_NOT_DELAY_SLOT \
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
- {gen_op_raise_slot_illegal_instruction (); ctx->flags |= BRANCH_EXCEPTION; \
+ {gen_op_raise_slot_illegal_instruction (); ctx->bstate = BS_EXCP; \
return;}
-void decode_opc(DisasContext * ctx)
+void _decode_opc(DisasContext * ctx)
{
#if 0
fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
gen_op_clrt();
return;
case 0x0038: /* ldtlb */
+#if defined(CONFIG_USER_ONLY)
assert(0); /* XXXXX */
+#else
+ gen_op_ldtlb();
+#endif
return;
case 0x002b: /* rte */
CHECK_NOT_DELAY_SLOT gen_op_rte();
case 0x0018: /* sett */
gen_op_sett();
return;
- case 0xfbfb: /* frchg */
+ case 0xfbfd: /* frchg */
gen_op_frchg();
- ctx->flags |= MODE_CHANGE;
+ ctx->bstate = BS_STOP;
return;
- case 0xf3fb: /* fschg */
+ case 0xf3fd: /* fschg */
gen_op_fschg();
- ctx->flags |= MODE_CHANGE;
+ ctx->bstate = BS_STOP;
return;
case 0x0009: /* nop */
return;
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
- case 0xe000: /* mov.l #imm,Rn */
+ case 0xe000: /* mov #imm,Rn */
gen_op_movl_imm_rN(B7_0s, REG(B11_8));
return;
case 0x9000: /* mov.w @(disp,PC),Rn */
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
- case 0x7000: /* add.l #imm,Rn */
+ case 0x7000: /* add #imm,Rn */
gen_op_add_imm_rN(B7_0s, REG(B11_8));
return;
case 0xa000: /* bra disp */
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x2004: /* mov.b Rm,@-Rn */
- gen_op_dec1_rN(REG(B11_8));
gen_op_movl_rN_T0(REG(B7_4));
+ gen_op_dec1_rN(REG(B11_8));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stb_T0_T1(ctx);
return;
case 0x2005: /* mov.w Rm,@-Rn */
- gen_op_dec2_rN(REG(B11_8));
gen_op_movl_rN_T0(REG(B7_4));
+ gen_op_dec2_rN(REG(B11_8));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stw_T0_T1(ctx);
return;
case 0x2006: /* mov.l Rm,@-Rn */
- gen_op_dec4_rN(REG(B11_8));
gen_op_movl_rN_T0(REG(B7_4));
+ gen_op_dec4_rN(REG(B11_8));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stl_T0_T1(ctx);
return;
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldb_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
- gen_op_inc1_rN(REG(B7_4));
+ if ( B11_8 != B7_4 )
+ gen_op_inc1_rN(REG(B7_4));
return;
case 0x6005: /* mov.w @Rm+,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldw_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
- gen_op_inc2_rN(REG(B7_4));
+ if ( B11_8 != B7_4 )
+ gen_op_inc2_rN(REG(B7_4));
return;
case 0x6006: /* mov.l @Rm+,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
- gen_op_inc4_rN(REG(B7_4));
+ if ( B11_8 != B7_4 )
+ gen_op_inc4_rN(REG(B7_4));
return;
case 0x0004: /* mov.b Rm,@(R0,Rn) */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_div0s_T0_T1();
- gen_op_movl_T1_rN(REG(B11_8));
return;
case 0x3004: /* div1 Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movuw_rN_T0(REG(B7_4));
gen_op_movl_T0_rN(REG(B11_8));
return;
- case 0x000f: /* mac.l @Rm+,@Rn- */
+ case 0x000f: /* mac.l @Rm+,@Rn+ */
gen_op_movl_rN_T0(REG(B11_8));
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_T1();
- gen_op_movl_rN_T1(REG(B7_4));
+ gen_op_inc4_rN(REG(B11_8));
+ gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldl_T0_T0(ctx);
gen_op_macl_T0_T1();
gen_op_inc4_rN(REG(B7_4));
- gen_op_inc4_rN(REG(B11_8));
return;
case 0x400f: /* mac.w @Rm+,@Rn+ */
gen_op_movl_rN_T0(REG(B11_8));
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_T1();
- gen_op_movl_rN_T1(REG(B7_4));
+ gen_op_inc2_rN(REG(B11_8));
+ gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldl_T0_T0(ctx);
gen_op_macw_T0_T1();
gen_op_inc2_rN(REG(B7_4));
- gen_op_inc2_rN(REG(B11_8));
return;
case 0x0007: /* mul.l Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
return;
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- if (ctx->opcode & 0x0110)
- break; /* illegal instruction */
- gen_op_fmov_drN_DT0(DREG(B7_4));
- gen_op_fmov_DT0_drN(DREG(B11_8));
+ gen_op_fmov_drN_DT0(XREG(B7_4));
+ gen_op_fmov_DT0_drN(XREG(B11_8));
} else {
gen_op_fmov_frN_FT0(FREG(B7_4));
gen_op_fmov_FT0_frN(FREG(B11_8));
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- if (ctx->opcode & 0x0010)
- break; /* illegal instruction */
- gen_op_fmov_drN_DT0(DREG(B7_4));
+ gen_op_fmov_drN_DT0(XREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stfq_DT0_T1(ctx);
} else {
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- if (ctx->opcode & 0x0100)
- break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfq_T0_DT0(ctx);
- gen_op_fmov_DT0_drN(DREG(B11_8));
+ gen_op_fmov_DT0_drN(XREG(B11_8));
} else {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfl_T0_FT0(ctx);
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- if (ctx->opcode & 0x0100)
- break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfq_T0_DT0(ctx);
- gen_op_fmov_DT0_drN(DREG(B11_8));
+ gen_op_fmov_DT0_drN(XREG(B11_8));
gen_op_inc8_rN(REG(B7_4));
} else {
gen_op_movl_rN_T0(REG(B7_4));
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- if (ctx->opcode & 0x0100)
- break; /* illegal instruction */
gen_op_dec8_rN(REG(B11_8));
- gen_op_fmov_drN_DT0(DREG(B7_4));
+ gen_op_fmov_drN_DT0(XREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stfq_DT0_T1(ctx);
} else {
return;
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- if (ctx->opcode & 0x0100)
- break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
gen_op_ldfq_T0_DT0(ctx);
- gen_op_fmov_DT0_drN(DREG(B11_8));
+ gen_op_fmov_DT0_drN(XREG(B11_8));
} else {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
return;
case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
- if (ctx->opcode & 0x0010)
- break; /* illegal instruction */
- gen_op_fmov_drN_DT0(DREG(B7_4));
+ gen_op_fmov_drN_DT0(XREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_add_rN_T1(REG(0));
gen_op_stfq_DT0_T1(ctx);
ctx->fpscr & FPSCR_PR ? gen_op_fdiv_DT() : gen_op_fdiv_FT();
break;
case 0xf004: /* fcmp/eq Rm,Rn */
+ ctx->fpscr & FPSCR_PR ? gen_op_fcmp_eq_DT() : gen_op_fcmp_eq_FT();
return;
case 0xf005: /* fcmp/gt Rm,Rn */
+ ctx->fpscr & FPSCR_PR ? gen_op_fcmp_gt_DT() : gen_op_fcmp_gt_FT();
return;
}
case 0xc900: /* and #imm,R0 */
gen_op_and_imm_rN(B7_0, REG(0));
return;
- case 0xcd00: /* and.b #imm,@(R0+GBR) */
+ case 0xcd00: /* and.b #imm,@(R0,GBR) */
gen_op_movl_rN_T0(REG(0));
gen_op_addl_GBR_T0();
gen_op_movl_T0_T1();
- gen_op_ldb_T0_T0(ctx);
+ gen_op_ldub_T0_T0(ctx);
gen_op_and_imm_T0(B7_0);
gen_op_stb_T0_T1(ctx);
return;
CHECK_NOT_DELAY_SLOT
gen_conditional_jump(ctx, ctx->pc + 2,
ctx->pc + 4 + B7_0s * 2);
- ctx->flags |= BRANCH_CONDITIONAL;
+ ctx->bstate = BS_BRANCH;
return;
case 0x8f00: /* bf/s label */
CHECK_NOT_DELAY_SLOT
CHECK_NOT_DELAY_SLOT
gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
ctx->pc + 2);
- ctx->flags |= BRANCH_CONDITIONAL;
+ ctx->bstate = BS_BRANCH;
return;
case 0x8d00: /* bt/s label */
CHECK_NOT_DELAY_SLOT
return;
case 0xc500: /* mov.w @(disp,GBR),R0 */
gen_op_stc_gbr_T0();
- gen_op_addl_imm_T0(B7_0);
+ gen_op_addl_imm_T0(B7_0 * 2);
gen_op_ldw_T0_T0(ctx);
gen_op_movl_T0_rN(REG(0));
return;
case 0xc600: /* mov.l @(disp,GBR),R0 */
gen_op_stc_gbr_T0();
- gen_op_addl_imm_T0(B7_0);
+ gen_op_addl_imm_T0(B7_0 * 4);
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(0));
return;
return;
case 0xc100: /* mov.w R0,@(disp,GBR) */
gen_op_stc_gbr_T0();
- gen_op_addl_imm_T0(B7_0);
+ gen_op_addl_imm_T0(B7_0 * 2);
gen_op_movl_T0_T1();
gen_op_movl_rN_T0(REG(0));
gen_op_stw_T0_T1(ctx);
return;
case 0xc200: /* mov.l R0,@(disp,GBR) */
gen_op_stc_gbr_T0();
- gen_op_addl_imm_T0(B7_0);
+ gen_op_addl_imm_T0(B7_0 * 4);
gen_op_movl_T0_T1();
gen_op_movl_rN_T0(REG(0));
gen_op_stl_T0_T1(ctx);
case 0xcb00: /* or #imm,R0 */
gen_op_or_imm_rN(B7_0, REG(0));
return;
- case 0xcf00: /* or.b #imm,@(R0+GBR) */
+ case 0xcf00: /* or.b #imm,@(R0,GBR) */
gen_op_movl_rN_T0(REG(0));
gen_op_addl_GBR_T0();
gen_op_movl_T0_T1();
- gen_op_ldb_T0_T0(ctx);
+ gen_op_ldub_T0_T0(ctx);
gen_op_or_imm_T0(B7_0);
gen_op_stb_T0_T1(ctx);
return;
case 0xc300: /* trapa #imm */
CHECK_NOT_DELAY_SLOT gen_op_movl_imm_PC(ctx->pc);
gen_op_trapa(B7_0);
- ctx->flags |= BRANCH;
+ ctx->bstate = BS_BRANCH;
return;
case 0xc800: /* tst #imm,R0 */
gen_op_tst_imm_rN(B7_0, REG(0));
return;
- case 0xcc00: /* tst #imm,@(R0+GBR) */
+ case 0xcc00: /* tst.b #imm,@(R0,GBR) */
gen_op_movl_rN_T0(REG(0));
gen_op_addl_GBR_T0();
- gen_op_ldb_T0_T0(ctx);
+ gen_op_ldub_T0_T0(ctx);
gen_op_tst_imm_T0(B7_0);
return;
case 0xca00: /* xor #imm,R0 */
gen_op_xor_imm_rN(B7_0, REG(0));
return;
- case 0xce00: /* xor.b #imm,@(R0+GBR) */
+ case 0xce00: /* xor.b #imm,@(R0,GBR) */
gen_op_movl_rN_T0(REG(0));
gen_op_addl_GBR_T0();
gen_op_movl_T0_T1();
- gen_op_ldb_T0_T0(ctx);
+ gen_op_ldub_T0_T0(ctx);
gen_op_xor_imm_T0(B7_0);
gen_op_stb_T0_T1(ctx);
return;
gen_op_movl_rN_T1 (REG(B11_8)); \
gen_op_stl_T0_T1 (ctx); \
return;
- LDST(sr, 0x400e, 0x4007, ldc, 0x0002, 0x4003, stc, ctx->flags |=
- MODE_CHANGE;)
+ LDST(sr, 0x400e, 0x4007, ldc, 0x0002, 0x4003, stc, ctx->bstate =
+ BS_STOP;)
LDST(gbr, 0x401e, 0x4017, ldc, 0x0012, 0x4013, stc,)
LDST(vbr, 0x402e, 0x4027, ldc, 0x0022, 0x4023, stc,)
LDST(ssr, 0x403e, 0x4037, ldc, 0x0032, 0x4033, stc,)
LDST(macl, 0x401a, 0x4016, lds, 0x001a, 0x4012, sts,)
LDST(pr, 0x402a, 0x4026, lds, 0x002a, 0x4022, sts,)
LDST(fpul, 0x405a, 0x4056, lds, 0x005a, 0x4052, sts,)
- LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->flags |=
- MODE_CHANGE;)
+ LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->bstate =
+ BS_STOP;)
case 0x00c3: /* movca.l R0,@Rm */
gen_op_movl_rN_T0(REG(0));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_movl_rN_T0(REG(B11_8));
gen_op_ldl_T0_T0(ctx);
return;
- case 0x00a2: /* ocbp @Rn */
+ case 0x00a3: /* ocbp @Rn */
gen_op_movl_rN_T0(REG(B11_8));
gen_op_ldl_T0_T0(ctx);
return;
gen_op_ftrc_FT();
}
return;
+ case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
+ gen_op_fneg_frN(FREG(B11_8));
+ return;
+ case 0xf05d: /* fabs FRn/DRn */
+ if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->opcode & 0x0100)
+ break; /* illegal instruction */
+ gen_op_fmov_drN_DT0(DREG(B11_8));
+ gen_op_fabs_DT();
+ gen_op_fmov_DT0_drN(DREG(B11_8));
+ } else {
+ gen_op_fmov_frN_FT0(FREG(B11_8));
+ gen_op_fabs_FT();
+ gen_op_fmov_FT0_frN(FREG(B11_8));
+ }
+ return;
+ case 0xf06d: /* fsqrt FRn */
+ if (ctx->fpscr & FPSCR_PR) {
+ if (ctx->opcode & 0x0100)
+ break; /* illegal instruction */
+ gen_op_fmov_drN_DT0(FREG(B11_8));
+ gen_op_fsqrt_DT();
+ gen_op_fmov_DT0_drN(FREG(B11_8));
+ } else {
+ gen_op_fmov_frN_FT0(FREG(B11_8));
+ gen_op_fsqrt_FT();
+ gen_op_fmov_FT0_frN(FREG(B11_8));
+ }
+ return;
+ case 0xf07d: /* fsrra FRn */
+ break;
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
if (!(ctx->fpscr & FPSCR_PR)) {
gen_op_movl_imm_T0(0);
return;
}
break;
+ case 0xf0ad: /* fcnvsd FPUL,DRn */
+ gen_op_movl_fpul_FT0();
+ gen_op_fcnvsd_FT_DT();
+ gen_op_fmov_DT0_drN(DREG(B11_8));
+ return;
+ case 0xf0bd: /* fcnvds DRn,FPUL */
+ gen_op_fmov_drN_DT0(DREG(B11_8));
+ gen_op_fcnvds_DT_FT();
+ gen_op_movl_FT0_fpul();
+ return;
}
fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
ctx->opcode, ctx->pc);
gen_op_raise_illegal_instruction();
- ctx->flags |= BRANCH_EXCEPTION;
+ ctx->bstate = BS_EXCP;
+}
+
+void decode_opc(DisasContext * ctx)
+{
+ uint32_t old_flags = ctx->flags;
+
+ _decode_opc(ctx);
+
+ if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
+ if (ctx->flags & DELAY_SLOT_CLEARME) {
+ gen_op_store_flags(0);
+ }
+ ctx->flags = 0;
+ ctx->bstate = BS_BRANCH;
+ if (old_flags & DELAY_SLOT_CONDITIONAL) {
+ gen_delayed_conditional_jump(ctx);
+ } else if (old_flags & DELAY_SLOT) {
+ gen_jump(ctx);
+ }
+
+ }
}
static inline int
DisasContext ctx;
target_ulong pc_start;
static uint16_t *gen_opc_end;
- uint32_t old_flags;
int i, ii;
+ int num_insns;
+ int max_insns;
pc_start = tb->pc;
- gen_opc_ptr = gen_opc_buf;
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
- gen_opparam_ptr = gen_opparam_buf;
ctx.pc = pc_start;
- ctx.flags = env->flags;
- old_flags = 0;
+ ctx.flags = (uint32_t)tb->flags;
+ ctx.bstate = BS_NONE;
ctx.sr = env->sr;
ctx.fpscr = env->fpscr;
ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
/* We don't know if the delayed pc came from a dynamic or static branch,
so assume it is a dynamic branch. */
- ctx.delayed_pc = -1;
+ ctx.delayed_pc = -1; /* use delayed pc from env pointer */
ctx.tb = tb;
ctx.singlestep_enabled = env->singlestep_enabled;
- nb_gen_labels = 0;
#ifdef DEBUG_DISAS
if (loglevel & CPU_LOG_TB_CPU) {
#endif
ii = -1;
- while ((old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) == 0 &&
- (ctx.flags & (BRANCH | BRANCH_CONDITIONAL | MODE_CHANGE |
- BRANCH_EXCEPTION)) == 0 &&
- gen_opc_ptr < gen_opc_end && ctx.sr == env->sr) {
- old_flags = ctx.flags;
+ num_insns = 0;
+ max_insns = tb->cflags & CF_COUNT_MASK;
+ if (max_insns == 0)
+ max_insns = CF_COUNT_MASK;
+ gen_icount_start();
+ while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
if (env->nb_breakpoints > 0) {
for (i = 0; i < env->nb_breakpoints; i++) {
if (ctx.pc == env->breakpoints[i]) {
/* We have hit a breakpoint - make sure PC is up-to-date */
gen_op_movl_imm_PC(ctx.pc);
gen_op_debug();
- ctx.flags |= BRANCH_EXCEPTION;
+ ctx.bstate = BS_EXCP;
break;
}
}
gen_opc_instr_start[ii++] = 0;
}
gen_opc_pc[ii] = ctx.pc;
+ gen_opc_hflags[ii] = ctx.flags;
gen_opc_instr_start[ii] = 1;
+ gen_opc_icount[ii] = num_insns;
}
+ if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
+ gen_io_start();
#if 0
fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
fflush(stderr);
#endif
ctx.opcode = lduw_code(ctx.pc);
decode_opc(&ctx);
+ num_insns++;
ctx.pc += 2;
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
if (env->singlestep_enabled)
break;
+ if (num_insns >= max_insns)
+ break;
#ifdef SH4_SINGLE_STEP
break;
#endif
}
-
- if (old_flags & DELAY_SLOT_CONDITIONAL) {
- gen_delayed_conditional_jump(&ctx);
- } else if (old_flags & DELAY_SLOT) {
- gen_op_clr_delay_slot();
- gen_jump(&ctx);
- } else if (ctx.flags & BRANCH_EXCEPTION) {
- gen_jump_exception(&ctx);
- } else if ((ctx.flags & (BRANCH | BRANCH_CONDITIONAL)) == 0) {
- gen_goto_tb(&ctx, 0, ctx.pc);
- }
-
+ if (tb->cflags & CF_LAST_IO)
+ gen_io_end();
if (env->singlestep_enabled) {
- gen_op_debug();
+ gen_op_debug();
+ } else {
+ switch (ctx.bstate) {
+ case BS_STOP:
+ /* gen_op_interrupt_restart(); */
+ /* fall through */
+ case BS_NONE:
+ if (ctx.flags) {
+ gen_op_store_flags(ctx.flags | DELAY_SLOT_CLEARME);
+ }
+ gen_goto_tb(&ctx, 0, ctx.pc);
+ break;
+ case BS_EXCP:
+ /* gen_op_interrupt_restart(); */
+ tcg_gen_exit_tb(0);
+ break;
+ case BS_BRANCH:
+ default:
+ break;
+ }
}
+
+ gen_icount_end(tb, num_insns);
*gen_opc_ptr = INDEX_op_end;
if (search_pc) {
i = gen_opc_ptr - gen_opc_buf;
gen_opc_instr_start[ii++] = 0;
} else {
tb->size = ctx.pc - pc_start;
+ tb->icount = num_insns;
}
#ifdef DEBUG_DISAS
target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
fprintf(logfile, "\n");
}
- if (loglevel & CPU_LOG_TB_OP) {
- fprintf(logfile, "OP:\n");
- dump_ops(gen_opc_buf, gen_opparam_buf);
- fprintf(logfile, "\n");
- }
#endif
return 0;
}
{
return gen_intermediate_code_internal(env, tb, 1);
}
+
+void gen_pc_load(CPUState *env, TranslationBlock *tb,
+ unsigned long searched_pc, int pc_pos, void *puc)
+{
+ env->pc = gen_opc_pc[pc_pos];
+ env->flags = gen_opc_hflags[pc_pos];
+}
projects / mirror_qemu.git / blobdiff