Sparc64: refactor kernel init

[mirror_qemu.git] / target-sparc / op_helper.c

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 9de74c46c2f4d1db0df878f178e32fb0c1b1e1e1..739ed9abd223c4e798c623d3d41ae66c7427a176 100644 (file)
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -13,22 +13,22 @@
 //#define DEBUG_PCALL
 
 #ifdef DEBUG_MMU
-#define DPRINTF_MMU(fmt, args...) \
-do { printf("MMU: " fmt , ##args); } while (0)
+#define DPRINTF_MMU(fmt, ...)                                   \
+    do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
 #else
-#define DPRINTF_MMU(fmt, args...) do {} while (0)
+#define DPRINTF_MMU(fmt, ...) do {} while (0)
 #endif
 
 #ifdef DEBUG_MXCC
-#define DPRINTF_MXCC(fmt, args...) \
-do { printf("MXCC: " fmt , ##args); } while (0)
+#define DPRINTF_MXCC(fmt, ...)                                  \
+    do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
 #else
-#define DPRINTF_MXCC(fmt, args...) do {} while (0)
+#define DPRINTF_MXCC(fmt, ...) do {} while (0)
 #endif
 
 #ifdef DEBUG_ASI
-#define DPRINTF_ASI(fmt, args...) \
-do { printf("ASI: " fmt , ##args); } while (0)
+#define DPRINTF_ASI(fmt, ...)                                   \
+    do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
 #endif
 
 #ifdef TARGET_SPARC64
@@ -1212,11 +1212,14 @@ GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
     defined(DEBUG_MXCC)
 static void dump_mxcc(CPUState *env)
 {
-    printf("mxccdata: %016llx %016llx %016llx %016llx\n",
+    printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
+           "\n",
            env->mxccdata[0], env->mxccdata[1],
            env->mxccdata[2], env->mxccdata[3]);
-    printf("mxccregs: %016llx %016llx %016llx %016llx\n"
-           "          %016llx %016llx %016llx %016llx\n",
+    printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
+           "\n"
+           "          %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
+           "\n",
            env->mxccregs[0], env->mxccregs[1],
            env->mxccregs[2], env->mxccregs[3],
            env->mxccregs[4], env->mxccregs[5],
@@ -1455,7 +1458,8 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
                 env->mmubpregs[reg] = 0ULL;
                 break;
             }
-            DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret);
+            DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
+                        ret);
         }
         break;
     case 8: /* User code access, XXX */
@@ -1808,7 +1812,7 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
                 env->mmubpregs[reg] = (val & 0xfULL);
                 break;
             }
-            DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg,
+            DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
                         env->mmuregs[reg]);
         }
         break;
@@ -1949,13 +1953,13 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
     case 0x89: // Secondary LE
         switch(size) {
         case 2:
-            addr = bswap16(addr);
+            val = bswap16(val);
             break;
         case 4:
-            addr = bswap32(addr);
+            val = bswap32(val);
             break;
         case 8:
-            addr = bswap64(addr);
+            val = bswap64(val);
             break;
         default:
             break;
@@ -2321,13 +2325,13 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
     case 0x89: // Secondary LE
         switch(size) {
         case 2:
-            addr = bswap16(addr);
+            val = bswap16(val);
             break;
         case 4:
-            addr = bswap32(addr);
+            val = bswap32(val);
             break;
         case 8:
-            addr = bswap64(addr);
+            val = bswap64(val);
             break;
         default:
             break;
@@ -3225,8 +3229,14 @@ static inline void change_pstate(uint64_t new_pstate)
     uint64_t pstate_regs, new_pstate_regs;
     uint64_t *src, *dst;
 
+    if (env->def->features & CPU_FEATURE_GL) {
+        // PS_AG is not implemented in this case
+        new_pstate &= ~PS_AG;
+    }
+
     pstate_regs = env->pstate & 0xc01;
     new_pstate_regs = new_pstate & 0xc01;
+
     if (new_pstate_regs != pstate_regs) {
         // Switch global register bank
         src = get_gregset(new_pstate_regs);
@@ -3239,8 +3249,7 @@ static inline void change_pstate(uint64_t new_pstate)
 
 void helper_wrpstate(target_ulong new_state)
 {
-    if (!(env->def->features & CPU_FEATURE_GL))
-        change_pstate(new_state & 0xf3f);
+    change_pstate(new_state & 0xf3f);
 }
 
 void helper_done(void)
@@ -3392,23 +3401,23 @@ void do_interrupt(CPUState *env)
     env->tsptr->tpc = env->pc;
     env->tsptr->tnpc = env->npc;
     env->tsptr->tt = intno;
-    if (!(env->def->features & CPU_FEATURE_GL)) {
-        switch (intno) {
-        case TT_IVEC:
-            change_pstate(PS_PEF | PS_PRIV | PS_IG);
-            break;
-        case TT_TFAULT:
-        case TT_TMISS:
-        case TT_DFAULT:
-        case TT_DMISS:
-        case TT_DPROT:
-            change_pstate(PS_PEF | PS_PRIV | PS_MG);
-            break;
-        default:
-            change_pstate(PS_PEF | PS_PRIV | PS_AG);
-            break;
-        }
+
+    switch (intno) {
+    case TT_IVEC:
+        change_pstate(PS_PEF | PS_PRIV | PS_IG);
+        break;
+    case TT_TFAULT:
+    case TT_TMISS:
+    case TT_DFAULT:
+    case TT_DMISS:
+    case TT_DPROT:
+        change_pstate(PS_PEF | PS_PRIV | PS_MG);
+        break;
+    default:
+        change_pstate(PS_PEF | PS_PRIV | PS_AG);
+        break;
     }
+
     if (intno == TT_CLRWIN)
         cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
     else if ((intno & 0x1c0) == TT_SPILL)