Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
+ License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include <stdarg.h>
/* global register indexes */
static TCGv_ptr cpu_env, cpu_regwptr;
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
+static TCGv_i32 cpu_cc_op;
static TCGv_i32 cpu_psr;
static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
static TCGv cpu_y;
#ifndef CONFIG_USER_ONLY
static TCGv cpu_tbr;
#endif
-static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
+static TCGv cpu_cond, cpu_dst, cpu_addr, cpu_val;
#ifdef TARGET_SPARC64
static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
static TCGv cpu_gsr;
/* Floating point registers */
static TCGv_i32 cpu_fpr[TARGET_FPREGS];
+static target_ulong gen_opc_npc[OPC_BUF_SIZE];
+static target_ulong gen_opc_jump_pc[2];
+
#include "gen-icount.h"
typedef struct DisasContext {
int mem_idx;
int fpu_enabled;
int address_mask_32bit;
+ int singlestep;
+ uint32_t cc_op; /* current CC operation */
struct TranslationBlock *tb;
sparc_def_t *def;
} DisasContext;
#define hypervisor(dc) 0
#endif
#else
-#define supervisor(dc) (dc->mem_idx >= 1)
+#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
#ifdef TARGET_SPARC64
-#define hypervisor(dc) (dc->mem_idx == 2)
+#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
#else
#endif
#endif
tb = s->tb;
if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
- (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
+ (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
+ !s->singlestep) {
/* jump to same page: we can use a direct jump */
tcg_gen_goto_tb(tb_num);
tcg_gen_movi_tl(cpu_pc, pc);
tcg_gen_andi_tl(reg, reg, 0x1);
}
-static inline void gen_cc_clear_icc(void)
-{
- tcg_gen_movi_i32(cpu_psr, 0);
-}
-
-#ifdef TARGET_SPARC64
-static inline void gen_cc_clear_xcc(void)
-{
- tcg_gen_movi_i32(cpu_xcc, 0);
-}
-#endif
-
-/* old op:
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
-*/
-static inline void gen_cc_NZ_icc(TCGv dst)
-{
- TCGv r_temp;
- int l1, l2;
-
- l1 = gen_new_label();
- l2 = gen_new_label();
- r_temp = tcg_temp_new();
- tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
- tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
- tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
- gen_set_label(l1);
- tcg_gen_ext32s_tl(r_temp, dst);
- tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
- tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
- gen_set_label(l2);
- tcg_temp_free(r_temp);
-}
-
-#ifdef TARGET_SPARC64
-static inline void gen_cc_NZ_xcc(TCGv dst)
-{
- int l1, l2;
-
- l1 = gen_new_label();
- l2 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
- gen_set_label(l1);
- tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
- gen_set_label(l2);
-}
-#endif
-
-/* old op:
- if (T0 < src1)
- env->psr |= PSR_CARRY;
-*/
-static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
-{
- TCGv r_temp1, r_temp2;
- int l1;
-
- l1 = gen_new_label();
- r_temp1 = tcg_temp_new();
- r_temp2 = tcg_temp_new();
- tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
- tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
- tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
- tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
- gen_set_label(l1);
- tcg_temp_free(r_temp1);
- tcg_temp_free(r_temp2);
-}
-
-#ifdef TARGET_SPARC64
-static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
-{
- int l1;
-
- l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
- gen_set_label(l1);
-}
-#endif
-
-/* old op:
- if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
- env->psr |= PSR_OVF;
-*/
-static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
-{
- TCGv r_temp;
-
- r_temp = tcg_temp_new();
- tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_not_tl(r_temp, r_temp);
- tcg_gen_xor_tl(cpu_tmp0, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
- tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
- tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
- tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
- tcg_temp_free(r_temp);
- tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
-}
-
-#ifdef TARGET_SPARC64
-static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
-{
- TCGv r_temp;
-
- r_temp = tcg_temp_new();
- tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_not_tl(r_temp, r_temp);
- tcg_gen_xor_tl(cpu_tmp0, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
- tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
- tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
- tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
- tcg_temp_free(r_temp);
- tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
-}
-#endif
-
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp;
tcg_temp_free(r_temp);
}
-static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
-{
- int l1;
-
- l1 = gen_new_label();
- tcg_gen_or_tl(cpu_tmp0, src1, src2);
- tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
- tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
- gen_set_label(l1);
-}
-
-static inline void gen_op_logic_cc(TCGv dst)
-{
- tcg_gen_mov_tl(cpu_cc_dst, dst);
-
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_NZ_xcc(cpu_cc_dst);
-#endif
-}
-
static inline void gen_tag_tv(TCGv src1, TCGv src2)
{
int l1;
gen_set_label(l1);
}
-static inline void gen_op_add_cc2(TCGv dst)
-{
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
- tcg_gen_mov_tl(dst, cpu_cc_dst);
-}
-
static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_movi_tl(cpu_cc_src2, src2);
tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2);
- gen_op_add_cc2(dst);
+ tcg_gen_mov_tl(dst, cpu_cc_dst);
}
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_op_add_cc2(dst);
+ tcg_gen_mov_tl(dst, cpu_cc_dst);
}
-static inline void gen_op_addx_cc2(TCGv dst)
+static TCGv_i32 gen_add32_carry32(void)
{
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
+ TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
+
+ /* Carry is computed from a previous add: (dst < src) */
+#if TARGET_LONG_BITS == 64
+ cc_src1_32 = tcg_temp_new_i32();
+ cc_src2_32 = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_dst);
+ tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src);
+#else
+ cc_src1_32 = cpu_cc_dst;
+ cc_src2_32 = cpu_cc_src;
#endif
- tcg_gen_mov_tl(dst, cpu_cc_dst);
+
+ carry_32 = tcg_temp_new_i32();
+ tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
+
+#if TARGET_LONG_BITS == 64
+ tcg_temp_free_i32(cc_src1_32);
+ tcg_temp_free_i32(cc_src2_32);
+#endif
+
+ return carry_32;
}
-static inline void gen_op_addxi_cc(TCGv dst, TCGv src1, target_long src2)
+static TCGv_i32 gen_sub32_carry32(void)
{
- tcg_gen_mov_tl(cpu_cc_src, src1);
- tcg_gen_movi_tl(cpu_cc_src2, src2);
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
- gen_cc_clear_icc();
- gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
+ TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
+
+ /* Carry is computed from a previous borrow: (src1 < src2) */
+#if TARGET_LONG_BITS == 64
+ cc_src1_32 = tcg_temp_new_i32();
+ cc_src2_32 = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_src);
+ tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src2);
+#else
+ cc_src1_32 = cpu_cc_src;
+ cc_src2_32 = cpu_cc_src2;
+#endif
+
+ carry_32 = tcg_temp_new_i32();
+ tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
+
+#if TARGET_LONG_BITS == 64
+ tcg_temp_free_i32(cc_src1_32);
+ tcg_temp_free_i32(cc_src2_32);
#endif
- tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_dst, src2);
- gen_op_addx_cc2(dst);
+
+ return carry_32;
}
-static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
+static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
+ TCGv src2, int update_cc)
{
- tcg_gen_mov_tl(cpu_cc_src, src1);
- tcg_gen_mov_tl(cpu_cc_src2, src2);
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
- gen_cc_clear_icc();
- gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
+ TCGv_i32 carry_32;
+ TCGv carry;
+
+ switch (dc->cc_op) {
+ case CC_OP_DIV:
+ case CC_OP_LOGIC:
+ /* Carry is known to be zero. Fall back to plain ADD. */
+ if (update_cc) {
+ gen_op_add_cc(dst, src1, src2);
+ } else {
+ tcg_gen_add_tl(dst, src1, src2);
+ }
+ return;
+
+ case CC_OP_ADD:
+ case CC_OP_TADD:
+ case CC_OP_TADDTV:
+#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
+ {
+ /* For 32-bit hosts, we can re-use the host's hardware carry
+ generation by using an ADD2 opcode. We discard the low
+ part of the output. Ideally we'd combine this operation
+ with the add that generated the carry in the first place. */
+ TCGv dst_low = tcg_temp_new();
+ tcg_gen_op6_i32(INDEX_op_add2_i32, dst_low, dst,
+ cpu_cc_src, src1, cpu_cc_src2, src2);
+ tcg_temp_free(dst_low);
+ goto add_done;
+ }
+#endif
+ carry_32 = gen_add32_carry32();
+ break;
+
+ case CC_OP_SUB:
+ case CC_OP_TSUB:
+ case CC_OP_TSUBTV:
+ carry_32 = gen_sub32_carry32();
+ break;
+
+ default:
+ /* We need external help to produce the carry. */
+ carry_32 = tcg_temp_new_i32();
+ gen_helper_compute_C_icc(carry_32);
+ break;
+ }
+
+#if TARGET_LONG_BITS == 64
+ carry = tcg_temp_new();
+ tcg_gen_extu_i32_i64(carry, carry_32);
+#else
+ carry = carry_32;
#endif
- tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
- gen_op_addx_cc2(dst);
+
+ tcg_gen_add_tl(dst, src1, src2);
+ tcg_gen_add_tl(dst, dst, carry);
+
+ tcg_temp_free_i32(carry_32);
+#if TARGET_LONG_BITS == 64
+ tcg_temp_free(carry);
+#endif
+
+#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
+ add_done:
+#endif
+ if (update_cc) {
+ tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
+ dc->cc_op = CC_OP_ADDX;
+ }
}
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
gen_tag_tv(cpu_cc_src, cpu_cc_src2);
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
-/* old op:
- if (src1 < T1)
- env->psr |= PSR_CARRY;
-*/
-static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
-{
- TCGv r_temp1, r_temp2;
- int l1;
-
- l1 = gen_new_label();
- r_temp1 = tcg_temp_new();
- r_temp2 = tcg_temp_new();
- tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
- tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
- tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
- tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
- gen_set_label(l1);
- tcg_temp_free(r_temp1);
- tcg_temp_free(r_temp2);
-}
-
-#ifdef TARGET_SPARC64
-static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
-{
- int l1;
-
- l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
- tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
- gen_set_label(l1);
-}
-#endif
-
-/* old op:
- if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
- env->psr |= PSR_OVF;
-*/
-static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
-{
- TCGv r_temp;
-
- r_temp = tcg_temp_new();
- tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xor_tl(cpu_tmp0, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
- tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
- tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
- tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
- tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
- tcg_temp_free(r_temp);
-}
-
-#ifdef TARGET_SPARC64
-static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
-{
- TCGv r_temp;
-
- r_temp = tcg_temp_new();
- tcg_gen_xor_tl(r_temp, src1, src2);
- tcg_gen_xor_tl(cpu_tmp0, src1, dst);
- tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
- tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
- tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
- tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
- tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
- tcg_temp_free(r_temp);
-}
-#endif
-
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
{
TCGv r_temp;
tcg_temp_free(r_temp);
}
-static inline void gen_op_sub_cc2(TCGv dst)
-{
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
- gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
- gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
- tcg_gen_mov_tl(dst, cpu_cc_dst);
-}
-
-static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2)
+static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_movi_tl(cpu_cc_src2, src2);
if (src2 == 0) {
- tcg_gen_mov_tl(dst, src1);
- gen_op_logic_cc(dst);
+ tcg_gen_mov_tl(cpu_cc_dst, src1);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
} else {
tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);
- gen_op_sub_cc2(dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
+ dc->cc_op = CC_OP_SUB;
}
+ tcg_gen_mov_tl(dst, cpu_cc_dst);
}
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_op_sub_cc2(dst);
+ tcg_gen_mov_tl(dst, cpu_cc_dst);
}
-static inline void gen_op_subx_cc2(TCGv dst)
+static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
+ TCGv src2, int update_cc)
{
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
+ TCGv_i32 carry_32;
+ TCGv carry;
+
+ switch (dc->cc_op) {
+ case CC_OP_DIV:
+ case CC_OP_LOGIC:
+ /* Carry is known to be zero. Fall back to plain SUB. */
+ if (update_cc) {
+ gen_op_sub_cc(dst, src1, src2);
+ } else {
+ tcg_gen_sub_tl(dst, src1, src2);
+ }
+ return;
+
+ case CC_OP_ADD:
+ case CC_OP_TADD:
+ case CC_OP_TADDTV:
+ carry_32 = gen_add32_carry32();
+ break;
+
+ case CC_OP_SUB:
+ case CC_OP_TSUB:
+ case CC_OP_TSUBTV:
+#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
+ {
+ /* For 32-bit hosts, we can re-use the host's hardware carry
+ generation by using a SUB2 opcode. We discard the low
+ part of the output. Ideally we'd combine this operation
+ with the add that generated the carry in the first place. */
+ TCGv dst_low = tcg_temp_new();
+ tcg_gen_op6_i32(INDEX_op_sub2_i32, dst_low, dst,
+ cpu_cc_src, src1, cpu_cc_src2, src2);
+ tcg_temp_free(dst_low);
+ goto sub_done;
+ }
#endif
- tcg_gen_mov_tl(dst, cpu_cc_dst);
-}
+ carry_32 = gen_sub32_carry32();
+ break;
-static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2)
-{
- tcg_gen_mov_tl(cpu_cc_src, src1);
- tcg_gen_movi_tl(cpu_cc_src2, src2);
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
- gen_cc_clear_icc();
- gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
+ default:
+ /* We need external help to produce the carry. */
+ carry_32 = tcg_temp_new_i32();
+ gen_helper_compute_C_icc(carry_32);
+ break;
+ }
+
+#if TARGET_LONG_BITS == 64
+ carry = tcg_temp_new();
+ tcg_gen_extu_i32_i64(carry, carry_32);
+#else
+ carry = carry_32;
#endif
- tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2);
- gen_op_subx_cc2(dst);
-}
-static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
-{
- tcg_gen_mov_tl(cpu_cc_src, src1);
- tcg_gen_mov_tl(cpu_cc_src2, src2);
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
- gen_cc_clear_icc();
- gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
+ tcg_gen_sub_tl(dst, src1, src2);
+ tcg_gen_sub_tl(dst, dst, carry);
+
+ tcg_temp_free_i32(carry_32);
+#if TARGET_LONG_BITS == 64
+ tcg_temp_free(carry);
+#endif
+
+#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
+ sub_done:
#endif
- tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
- gen_op_subx_cc2(dst);
+ if (update_cc) {
+ tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_mov_tl(cpu_cc_src2, src2);
+ tcg_gen_mov_tl(cpu_cc_dst, dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
+ dc->cc_op = CC_OP_SUBX;
+ }
}
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
- gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
- gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
gen_tag_tv(cpu_cc_src, cpu_cc_src2);
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
- gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
- /* do addition and update flags */
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
-static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
+static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
{
+ TCGv_i32 r_src1, r_src2;
TCGv_i64 r_temp, r_temp2;
+ r_src1 = tcg_temp_new_i32();
+ r_src2 = tcg_temp_new_i32();
+
+ tcg_gen_trunc_tl_i32(r_src1, src1);
+ tcg_gen_trunc_tl_i32(r_src2, src2);
+
r_temp = tcg_temp_new_i64();
r_temp2 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(r_temp, src2);
- tcg_gen_extu_tl_i64(r_temp2, src1);
+ if (sign_ext) {
+ tcg_gen_ext_i32_i64(r_temp, r_src2);
+ tcg_gen_ext_i32_i64(r_temp2, r_src1);
+ } else {
+ tcg_gen_extu_i32_i64(r_temp, r_src2);
+ tcg_gen_extu_i32_i64(r_temp2, r_src1);
+ }
+
tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
tcg_gen_shri_i64(r_temp, r_temp2, 32);
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
tcg_temp_free_i64(r_temp);
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
-#ifdef TARGET_SPARC64
- tcg_gen_mov_i64(dst, r_temp2);
-#else
+
tcg_gen_trunc_i64_tl(dst, r_temp2);
-#endif
+
tcg_temp_free_i64(r_temp2);
+
+ tcg_temp_free_i32(r_src1);
+ tcg_temp_free_i32(r_src2);
}
-static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
+static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
{
- TCGv_i64 r_temp, r_temp2;
-
- r_temp = tcg_temp_new_i64();
- r_temp2 = tcg_temp_new_i64();
-
- tcg_gen_ext_tl_i64(r_temp, src2);
- tcg_gen_ext_tl_i64(r_temp2, src1);
- tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
+ /* zero-extend truncated operands before multiplication */
+ gen_op_multiply(dst, src1, src2, 0);
+}
- tcg_gen_shri_i64(r_temp, r_temp2, 32);
- tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
- tcg_temp_free_i64(r_temp);
- tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
-#ifdef TARGET_SPARC64
- tcg_gen_mov_i64(dst, r_temp2);
-#else
- tcg_gen_trunc_i64_tl(dst, r_temp2);
-#endif
- tcg_temp_free_i64(r_temp2);
+static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
+{
+ /* sign-extend truncated operands before multiplication */
+ gen_op_multiply(dst, src1, src2, 1);
}
#ifdef TARGET_SPARC64
}
#endif
-static inline void gen_op_div_cc(TCGv dst)
-{
- int l1;
-
- tcg_gen_mov_tl(cpu_cc_dst, dst);
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
- l1 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
- tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
- gen_set_label(l1);
-}
-
// 1
static inline void gen_op_eval_ba(TCGv dst)
{
static inline void save_state(DisasContext *dc, TCGv cond)
{
tcg_gen_movi_tl(cpu_pc, dc->pc);
+ /* flush pending conditional evaluations before exposing cpu state */
+ if (dc->cc_op != CC_OP_FLAGS) {
+ dc->cc_op = CC_OP_FLAGS;
+ gen_helper_compute_psr();
+ }
save_npc(dc, cond);
}
tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
}
-static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
+static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
+ DisasContext *dc)
{
TCGv_i32 r_src;
#else
r_src = cpu_psr;
#endif
+ switch (dc->cc_op) {
+ case CC_OP_FLAGS:
+ break;
+ default:
+ gen_helper_compute_psr();
+ dc->cc_op = CC_OP_FLAGS;
+ break;
+ }
switch (cond) {
case 0x0:
gen_op_eval_bn(r_dst);
} else {
dc->pc = dc->npc;
dc->npc = target;
+ tcg_gen_mov_tl(cpu_pc, cpu_npc);
}
} else {
flush_cond(dc, r_cond);
- gen_cond(r_cond, cc, cond);
+ gen_cond(r_cond, cc, cond, dc);
if (a) {
gen_branch_a(dc, target, dc->npc, r_cond);
dc->is_br = 1;
} else {
dc->pc = dc->npc;
dc->npc = target;
+ tcg_gen_mov_tl(cpu_pc, cpu_npc);
}
} else {
flush_cond(dc, r_cond);
unsigned int rs1;
rs1 = GET_FIELD(insn, 13, 17);
- if (rs1 == 0)
- r_rs1 = tcg_const_tl(0); // XXX how to free?
- else if (rs1 < 8)
+ if (rs1 == 0) {
+ tcg_gen_movi_tl(def, 0);
+ } else if (rs1 < 8) {
r_rs1 = cpu_gregs[rs1];
- else
+ } else {
tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
+ }
return r_rs1;
}
TCGv r_rs2 = def;
if (IS_IMM) { /* immediate */
- target_long simm;
-
- simm = GET_FIELDs(insn, 19, 31);
- r_rs2 = tcg_const_tl(simm); // XXX how to free?
+ target_long simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_movi_tl(def, simm);
} else { /* register */
- unsigned int rs2;
-
- rs2 = GET_FIELD(insn, 27, 31);
- if (rs2 == 0)
- r_rs2 = tcg_const_tl(0); // XXX how to free?
- else if (rs2 < 8)
+ unsigned int rs2 = GET_FIELD(insn, 27, 31);
+ if (rs2 == 0) {
+ tcg_gen_movi_tl(def, 0);
+ } else if (rs2 < 8) {
r_rs2 = cpu_gregs[rs2];
- else
+ } else {
tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
+ }
}
return r_rs2;
}
+#ifdef TARGET_SPARC64
+static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
+{
+ TCGv_i32 r_tl = tcg_temp_new_i32();
+
+ /* load env->tl into r_tl */
+ tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
+
+ /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
+ tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
+
+ /* calculate offset to current trap state from env->ts, reuse r_tl */
+ tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
+ tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUState, ts));
+
+ /* tsptr = env->ts[env->tl & MAXTL_MASK] */
+ {
+ TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
+ tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
+ tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
+ tcg_temp_free_ptr(r_tl_tmp);
+ }
+
+ tcg_temp_free_i32(r_tl);
+}
+#endif
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
static void disas_sparc_insn(DisasContext * dc)
{
unsigned int insn, opc, rs1, rs2, rd;
+ TCGv cpu_src1, cpu_src2, cpu_tmp1, cpu_tmp2;
target_long simm;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
rd = GET_FIELD(insn, 2, 6);
- cpu_src1 = tcg_temp_new(); // const
- cpu_src2 = tcg_temp_new(); // const
+ cpu_tmp1 = cpu_src1 = tcg_temp_new();
+ cpu_tmp2 = cpu_src2 = tcg_temp_new();
switch (opc) {
case 0: /* branches/sethi */
save_state(dc, cpu_cond);
if (cc == 0)
- gen_cond(r_cond, 0, cond);
+ gen_cond(r_cond, 0, cond, dc);
else if (cc == 2)
- gen_cond(r_cond, 1, cond);
+ gen_cond(r_cond, 1, cond, dc);
else
goto illegal_insn;
#else
save_state(dc, cpu_cond);
- gen_cond(r_cond, 0, cond);
+ gen_cond(r_cond, 0, cond, dc);
#endif
l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
break;
#ifdef TARGET_SPARC64
case 0x2: /* V9 rdccr */
+ gen_helper_compute_psr();
gen_helper_rdccr(cpu_dst);
gen_movl_TN_reg(rd, cpu_dst);
break;
#ifndef TARGET_SPARC64
if (!supervisor(dc))
goto priv_insn;
+ gen_helper_compute_psr();
+ dc->cc_op = CC_OP_FLAGS;
gen_helper_rdpsr(cpu_dst);
#else
CHECK_IU_FEATURE(dc, HYPV);
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tsptr, cpu_env,
- offsetof(CPUState, tsptr));
+ gen_load_trap_state_at_tl(r_tsptr, cpu_env);
tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tpc));
tcg_temp_free_ptr(r_tsptr);
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tsptr, cpu_env,
- offsetof(CPUState, tsptr));
+ gen_load_trap_state_at_tl(r_tsptr, cpu_env);
tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tnpc));
tcg_temp_free_ptr(r_tsptr);
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tsptr, cpu_env,
- offsetof(CPUState, tsptr));
+ gen_load_trap_state_at_tl(r_tsptr, cpu_env);
tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tstate));
tcg_temp_free_ptr(r_tsptr);
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tsptr, cpu_env,
- offsetof(CPUState, tsptr));
+ gen_load_trap_state_at_tl(r_tsptr, cpu_env);
tcg_gen_ld_i32(cpu_tmp32, r_tsptr,
offsetof(trap_state, tt));
tcg_temp_free_ptr(r_tsptr);
rs1 = GET_FIELD(insn, 13, 17);
rs2 = GET_FIELD(insn, 27, 31);
xop = GET_FIELD(insn, 18, 26);
+ save_state(dc, cpu_cond);
switch (xop) {
case 0x1: /* fmovs */
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
rs1 = GET_FIELD(insn, 13, 17);
rs2 = GET_FIELD(insn, 27, 31);
xop = GET_FIELD(insn, 18, 26);
+ save_state(dc, cpu_cond);
#ifdef TARGET_SPARC64
if ((xop & 0x11f) == 0x005) { // V9 fmovsr
int l1;
l1 = gen_new_label(); \
r_cond = tcg_temp_new(); \
cond = GET_FIELD_SP(insn, 14, 17); \
- gen_cond(r_cond, icc, cond); \
+ gen_cond(r_cond, icc, cond, dc); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
0, l1); \
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \
l1 = gen_new_label(); \
r_cond = tcg_temp_new(); \
cond = GET_FIELD_SP(insn, 14, 17); \
- gen_cond(r_cond, icc, cond); \
+ gen_cond(r_cond, icc, cond, dc); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
0, l1); \
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \
l1 = gen_new_label(); \
r_cond = tcg_temp_new(); \
cond = GET_FIELD_SP(insn, 14, 17); \
- gen_cond(r_cond, icc, cond); \
+ gen_cond(r_cond, icc, cond, dc); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
0, l1); \
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \
simm = GET_FIELDs(insn, 19, 31);
if (xop & 0x10) {
gen_op_addi_cc(cpu_dst, cpu_src1, simm);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
+ dc->cc_op = CC_OP_ADD;
} else {
tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
}
} else {
if (xop & 0x10) {
gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
+ dc->cc_op = CC_OP_ADD;
} else {
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
}
tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
}
if (xop & 0x10) {
- gen_op_logic_cc(cpu_dst);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
}
break;
case 0x2: /* or */
} else {
tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
}
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
case 0x3: /* xor */
if (IS_IMM) {
} else {
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
}
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
case 0x4: /* sub */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
if (xop & 0x10) {
- gen_op_subi_cc(cpu_dst, cpu_src1, simm);
+ gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc);
} else {
tcg_gen_subi_tl(cpu_dst, cpu_src1, simm);
}
} else {
if (xop & 0x10) {
gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
+ dc->cc_op = CC_OP_SUB;
} else {
tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
}
} else {
tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
}
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
case 0x6: /* orn */
if (IS_IMM) {
} else {
tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
}
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
case 0x7: /* xorn */
if (IS_IMM) {
tcg_gen_not_tl(cpu_tmp0, cpu_src2);
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
case 0x8: /* addx, V9 addc */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- if (xop & 0x10)
- gen_op_addxi_cc(cpu_dst, cpu_src1, simm);
- else {
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm);
- tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
- }
- } else {
- if (xop & 0x10)
- gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
- else {
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
- tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
- }
- }
+ gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
+ (xop & 0x10));
break;
#ifdef TARGET_SPARC64
case 0x9: /* V9 mulx */
case 0xa: /* umul */
CHECK_IU_FEATURE(dc, MUL);
gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
case 0xb: /* smul */
CHECK_IU_FEATURE(dc, MUL);
gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
case 0xc: /* subx, V9 subc */
- if (IS_IMM) {
- simm = GET_FIELDs(insn, 19, 31);
- if (xop & 0x10) {
- gen_op_subxi_cc(cpu_dst, cpu_src1, simm);
- } else {
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm);
- tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
- }
- } else {
- if (xop & 0x10) {
- gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
- } else {
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
- tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
- }
- }
+ gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
+ (xop & 0x10));
break;
#ifdef TARGET_SPARC64
case 0xd: /* V9 udivx */
case 0xe: /* udiv */
CHECK_IU_FEATURE(dc, DIV);
gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_div_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV);
+ dc->cc_op = CC_OP_DIV;
+ }
break;
case 0xf: /* sdiv */
CHECK_IU_FEATURE(dc, DIV);
gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_div_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV);
+ dc->cc_op = CC_OP_DIV;
+ }
break;
default:
goto illegal_insn;
case 0x20: /* taddcc */
gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
+ dc->cc_op = CC_OP_TADD;
break;
case 0x21: /* tsubcc */
gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
+ dc->cc_op = CC_OP_TSUB;
break;
case 0x22: /* taddcctv */
save_state(dc, cpu_cond);
gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADDTV);
+ dc->cc_op = CC_OP_TADDTV;
break;
case 0x23: /* tsubcctv */
save_state(dc, cpu_cond);
gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUBTV);
+ dc->cc_op = CC_OP_TSUBTV;
break;
case 0x24: /* mulscc */
+ gen_helper_compute_psr();
gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
+ dc->cc_op = CC_OP_ADD;
break;
#ifndef TARGET_SPARC64
case 0x25: /* sll */
case 0x2: /* V9 wrccr */
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
gen_helper_wrccr(cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
break;
case 0x3: /* V9 wrasi */
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_andi_tl(cpu_dst, cpu_dst, 0xff);
tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst);
break;
case 0x6: /* V9 wrfprs */
break;
case 0xf: /* V9 sir, nop if user */
#if !defined(CONFIG_USER_ONLY)
- if (supervisor(dc))
+ if (supervisor(dc)) {
; // XXX
+ }
#endif
break;
case 0x13: /* Graphics Status */
#else
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
gen_helper_wrpsr(cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
save_state(dc, cpu_cond);
gen_op_next_insn();
tcg_gen_exit_tb(0);
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tsptr, cpu_env,
- offsetof(CPUState, tsptr));
+ gen_load_trap_state_at_tl(r_tsptr, cpu_env);
tcg_gen_st_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tpc));
tcg_temp_free_ptr(r_tsptr);
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tsptr, cpu_env,
- offsetof(CPUState, tsptr));
+ gen_load_trap_state_at_tl(r_tsptr, cpu_env);
tcg_gen_st_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tnpc));
tcg_temp_free_ptr(r_tsptr);
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tsptr, cpu_env,
- offsetof(CPUState, tsptr));
+ gen_load_trap_state_at_tl(r_tsptr, cpu_env);
tcg_gen_st_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state,
tstate));
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tsptr, cpu_env,
- offsetof(CPUState, tsptr));
+ gen_load_trap_state_at_tl(r_tsptr, cpu_env);
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp32, r_tsptr,
offsetof(trap_state, tt));
case 6: // pstate
save_state(dc, cpu_cond);
gen_helper_wrpstate(cpu_tmp0);
- gen_op_next_insn();
- tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->npc = DYNAMIC_PC;
break;
case 7: // tl
+ save_state(dc, cpu_cond);
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUSPARCState, tl));
+ dc->npc = DYNAMIC_PC;
break;
case 8: // pil
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState,
- psrpil));
+ gen_helper_wrpil(cpu_tmp0);
break;
case 9: // cwp
gen_helper_wrcwp(cpu_tmp0);
r_cond = tcg_temp_new();
if (insn & (1 << 18)) {
if (cc == 0)
- gen_cond(r_cond, 0, cond);
+ gen_cond(r_cond, 0, cond, dc);
else if (cc == 2)
- gen_cond(r_cond, 1, cond);
+ gen_cond(r_cond, 1, cond, dc);
else
goto illegal_insn;
} else {
{
unsigned int xop = GET_FIELD(insn, 7, 12);
+ /* flush pending conditional evaluations before exposing
+ cpu state */
+ if (dc->cc_op != CC_OP_FLAGS) {
+ dc->cc_op = CC_OP_FLAGS;
+ gen_helper_compute_psr();
+ }
cpu_src1 = get_src1(insn, cpu_src1);
if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
rs2 = GET_FIELD(insn, 27, 31);
if (rd == 1) {
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
gen_helper_ldxfsr(cpu_tmp64);
- } else
+ } else {
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
+ gen_helper_ldfsr(cpu_tmp32);
+ }
#else
{
tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
CHECK_FPU_FEATURE(dc, FLOAT128);
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_ldqf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_op_store_QT0_fpr(QFPREG(rd));
TCGv_i32 r_const;
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_lddf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_op_store_DT0_fpr(DFPREG(rd));
#endif
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 4);
+ dc->npc = DYNAMIC_PC;
break;
case 0x15: /* stba, store byte alternate */
#ifndef TARGET_SPARC64
#endif
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 1);
+ dc->npc = DYNAMIC_PC;
break;
case 0x16: /* stha, store halfword alternate */
#ifndef TARGET_SPARC64
#endif
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 2);
+ dc->npc = DYNAMIC_PC;
break;
case 0x17: /* stda, store double word alternate */
#ifndef TARGET_SPARC64
case 0x1e: /* V9 stxa */
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 8);
+ dc->npc = DYNAMIC_PC;
break;
#endif
default:
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rd));
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_stqf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
}
gen_op_load_fpr_DT0(DFPREG(rd));
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_stdf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
}
dc->npc = dc->npc + 4;
}
jmp_insn:
- return;
+ goto egress;
illegal_insn:
{
TCGv_i32 r_const;
tcg_temp_free_i32(r_const);
dc->is_br = 1;
}
- return;
+ goto egress;
unimp_flush:
{
TCGv_i32 r_const;
tcg_temp_free_i32(r_const);
dc->is_br = 1;
}
- return;
+ goto egress;
#if !defined(CONFIG_USER_ONLY)
priv_insn:
{
tcg_temp_free_i32(r_const);
dc->is_br = 1;
}
- return;
+ goto egress;
#endif
nfpu_insn:
save_state(dc, cpu_cond);
gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
dc->is_br = 1;
- return;
+ goto egress;
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
nfq_insn:
save_state(dc, cpu_cond);
gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
dc->is_br = 1;
- return;
+ goto egress;
#endif
#ifndef TARGET_SPARC64
ncp_insn:
tcg_temp_free(r_const);
dc->is_br = 1;
}
- return;
+ goto egress;
#endif
+ egress:
+ tcg_temp_free(cpu_tmp1);
+ tcg_temp_free(cpu_tmp2);
}
static inline void gen_intermediate_code_internal(TranslationBlock * tb,
dc->pc = pc_start;
last_pc = dc->pc;
dc->npc = (target_ulong) tb->cs_base;
+ dc->cc_op = CC_OP_DYNAMIC;
dc->mem_idx = cpu_mmu_index(env);
dc->def = env->def;
if ((dc->def->features & CPU_FEATURE_FLOAT))
#ifdef TARGET_SPARC64
dc->address_mask_32bit = env->pstate & PS_AM;
#endif
+ dc->singlestep = (env->singlestep_enabled || singlestep);
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cpu_tmp0 = tcg_temp_new();
max_insns = CF_COUNT_MASK;
gen_icount_start();
do {
- if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
- TAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
+ QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
if (bp->pc == dc->pc) {
if (dc->pc != pc_start)
save_state(dc, cpu_cond);
break;
/* if single step mode, we generate only one instruction and
generate an exception */
- if (env->singlestep_enabled || singlestep) {
- tcg_gen_movi_tl(cpu_pc, dc->pc);
- tcg_gen_exit_tb(0);
+ if (dc->singlestep) {
break;
}
} while ((gen_opc_ptr < gen_opc_end) &&
"cc_src2");
cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
"cc_dst");
+ cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op),
+ "cc_op");
cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr),
"psr");
cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr),
if (npc == 1) {
/* dynamic NPC: already stored */
} else if (npc == 2) {
- target_ulong t2 = (target_ulong)(unsigned long)puc;
- /* jump PC: use T2 and the jump targets of the translation */
- if (t2)
+ /* jump PC: use 'cond' and the jump targets of the translation */
+ if (env->cond) {
env->npc = gen_opc_jump_pc[0];
- else
+ } else {
env->npc = gen_opc_jump_pc[1];
+ }
} else {
env->npc = npc;
}
+
+ /* flush pending conditional evaluations before exposing cpu state */
+ if (CC_OP != CC_OP_FLAGS) {
+ helper_compute_psr();
+ }
}
projects / mirror_qemu.git / blobdiff