#include "qemu-common.h"
#include "exec/exec-all.h" /* MAX_OPC_PARAM_IARGS */
+#include "exec/cpu_ldst.h"
#include "tcg-op.h"
/* Marker for missing code. */
tcg_target_ulong);
#endif
-/* TCI can optionally use a global register variable for env. */
-#if !defined(AREG0)
-CPUArchState *env;
-#endif
-
/* Targets which don't use GETPC also don't need tci_tb_ptr
which makes them a little faster. */
#if defined(GETPC)
{
assert(index < ARRAY_SIZE(tci_reg));
assert(index != TCG_AREG0);
+ assert(index != TCG_REG_CALL_STACK);
tci_reg[index] = value;
}
-static void tci_write_reg8s(TCGReg index, int8_t value)
-{
- tci_write_reg(index, value);
-}
-
-static void tci_write_reg16s(TCGReg index, int16_t value)
-{
- tci_write_reg(index, value);
-}
-
#if TCG_TARGET_REG_BITS == 64
static void tci_write_reg32s(TCGReg index, int32_t value)
{
tci_write_reg(index, value);
}
-static void tci_write_reg16(TCGReg index, uint16_t value)
-{
- tci_write_reg(index, value);
-}
-
static void tci_write_reg32(TCGReg index, uint32_t value)
{
tci_write_reg(index, value);
return value;
}
-/* Read constant (32 bit) from bytecode. */
+/* Read unsigned constant (32 bit) from bytecode. */
static uint32_t tci_read_i32(uint8_t **tb_ptr)
{
uint32_t value = *(uint32_t *)(*tb_ptr);
return value;
}
+/* Read signed constant (32 bit) from bytecode. */
+static int32_t tci_read_s32(uint8_t **tb_ptr)
+{
+ int32_t value = *(int32_t *)(*tb_ptr);
+ *tb_ptr += sizeof(value);
+ return value;
+}
+
#if TCG_TARGET_REG_BITS == 64
/* Read constant (64 bit) from bytecode. */
static uint64_t tci_read_i64(uint8_t **tb_ptr)
return result;
}
+#ifdef CONFIG_SOFTMMU
+# define mmuidx tci_read_i(&tb_ptr)
+# define qemu_ld_ub \
+ helper_ret_ldub_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_ld_leuw \
+ helper_le_lduw_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_ld_leul \
+ helper_le_ldul_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_ld_leq \
+ helper_le_ldq_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_ld_beuw \
+ helper_be_lduw_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_ld_beul \
+ helper_be_ldul_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_ld_beq \
+ helper_be_ldq_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_st_b(X) \
+ helper_ret_stb_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_st_lew(X) \
+ helper_le_stw_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_st_lel(X) \
+ helper_le_stl_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_st_leq(X) \
+ helper_le_stq_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_st_bew(X) \
+ helper_be_stw_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_st_bel(X) \
+ helper_be_stl_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
+# define qemu_st_beq(X) \
+ helper_be_stq_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
+#else
+# define qemu_ld_ub ldub_p(g2h(taddr))
+# define qemu_ld_leuw lduw_le_p(g2h(taddr))
+# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
+# define qemu_ld_leq ldq_le_p(g2h(taddr))
+# define qemu_ld_beuw lduw_be_p(g2h(taddr))
+# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
+# define qemu_ld_beq ldq_be_p(g2h(taddr))
+# define qemu_st_b(X) stb_p(g2h(taddr), X)
+# define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
+# define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
+# define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
+# define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
+# define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
+# define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
+#endif
+
/* Interpret pseudo code in tb. */
-tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr)
+uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
{
- tcg_target_ulong next_tb = 0;
+ long tcg_temps[CPU_TEMP_BUF_NLONGS];
+ uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
+ uintptr_t next_tb = 0;
- env = cpustate;
tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
+ tci_reg[TCG_REG_CALL_STACK] = sp_value;
assert(tb_ptr);
for (;;) {
-#if defined(GETPC)
- tci_tb_ptr = (uintptr_t)tb_ptr;
-#endif
TCGOpcode opc = tb_ptr[0];
#if !defined(NDEBUG)
uint8_t op_size = tb_ptr[1];
tcg_target_ulong label;
TCGCond condition;
target_ulong taddr;
-#ifndef CONFIG_SOFTMMU
- tcg_target_ulong host_addr;
-#endif
uint8_t tmp8;
uint16_t tmp16;
uint32_t tmp32;
#if TCG_TARGET_REG_BITS == 32
uint64_t v64;
#endif
+ TCGMemOp memop;
+
+#if defined(GETPC)
+ tci_tb_ptr = (uintptr_t)tb_ptr;
+#endif
/* Skip opcode and size entry. */
tb_ptr += 2;
case INDEX_op_ld8u_i32:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i32:
case INDEX_op_ld_i32:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
break;
case INDEX_op_st8_i32:
t0 = tci_read_r8(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0;
break;
case INDEX_op_st16_i32:
t0 = tci_read_r16(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
*(uint16_t *)(t1 + t2) = t0;
break;
case INDEX_op_st_i32:
t0 = tci_read_r32(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
+ assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint32_t *)(t1 + t2) = t0;
break;
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
- tci_write_reg32(t0, t1 << t2);
+ tci_write_reg32(t0, t1 << (t2 & 31));
break;
case INDEX_op_shr_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
- tci_write_reg32(t0, t1 >> t2);
+ tci_write_reg32(t0, t1 >> (t2 & 31));
break;
case INDEX_op_sar_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
- tci_write_reg32(t0, ((int32_t)t1 >> t2));
+ tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31)));
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
- tci_write_reg32(t0, (t1 << t2) | (t1 >> (32 - t2)));
+ tci_write_reg32(t0, rol32(t1, t2 & 31));
break;
case INDEX_op_rotr_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
- tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2)));
+ tci_write_reg32(t0, ror32(t1, t2 & 31));
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
case INDEX_op_ld8u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i64:
case INDEX_op_ld32u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
break;
case INDEX_op_ld32s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
tci_write_reg32s(t0, *(int32_t *)(t1 + t2));
break;
case INDEX_op_ld_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
tci_write_reg64(t0, *(uint64_t *)(t1 + t2));
break;
case INDEX_op_st8_i64:
t0 = tci_read_r8(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0;
break;
case INDEX_op_st16_i64:
t0 = tci_read_r16(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
*(uint16_t *)(t1 + t2) = t0;
break;
case INDEX_op_st32_i64:
t0 = tci_read_r32(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
*(uint32_t *)(t1 + t2) = t0;
break;
case INDEX_op_st_i64:
t0 = tci_read_r64(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
- t2 = tci_read_i32(&tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
+ assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint64_t *)(t1 + t2) = t0;
break;
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
- tci_write_reg64(t0, t1 << t2);
+ tci_write_reg64(t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
- tci_write_reg64(t0, t1 >> t2);
+ tci_write_reg64(t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
- tci_write_reg64(t0, ((int64_t)t1 >> t2));
+ tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63)));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
+ t0 = *tb_ptr++;
+ t1 = tci_read_ri64(&tb_ptr);
+ t2 = tci_read_ri64(&tb_ptr);
+ tci_write_reg64(t0, rol64(t1, t2 & 63));
+ break;
case INDEX_op_rotr_i64:
- TODO();
+ t0 = *tb_ptr++;
+ t1 = tci_read_ri64(&tb_ptr);
+ t2 = tci_read_ri64(&tb_ptr);
+ tci_write_reg64(t0, ror64(t1, t2 & 63));
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
assert(tb_ptr == old_code_ptr + op_size);
tb_ptr += (int32_t)t0;
continue;
- case INDEX_op_qemu_ld8u:
- t0 = *tb_ptr++;
- taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr));
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- tmp8 = *(uint8_t *)(host_addr + GUEST_BASE);
-#endif
- tci_write_reg8(t0, tmp8);
- break;
- case INDEX_op_qemu_ld8s:
- t0 = *tb_ptr++;
- taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr));
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- tmp8 = *(uint8_t *)(host_addr + GUEST_BASE);
-#endif
- tci_write_reg8s(t0, tmp8);
- break;
- case INDEX_op_qemu_ld16u:
- t0 = *tb_ptr++;
- taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr));
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE));
-#endif
- tci_write_reg16(t0, tmp16);
- break;
- case INDEX_op_qemu_ld16s:
+ case INDEX_op_qemu_ld_i32:
t0 = *tb_ptr++;
taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr));
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE));
-#endif
- tci_write_reg16s(t0, tmp16);
- break;
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_qemu_ld32u:
- t0 = *tb_ptr++;
- taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
-#endif
- tci_write_reg32(t0, tmp32);
- break;
- case INDEX_op_qemu_ld32s:
- t0 = *tb_ptr++;
- taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
-#endif
- tci_write_reg32s(t0, tmp32);
- break;
-#endif /* TCG_TARGET_REG_BITS == 64 */
- case INDEX_op_qemu_ld32:
- t0 = *tb_ptr++;
- taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
-#endif
- tci_write_reg32(t0, tmp32);
+ memop = tci_read_i(&tb_ptr);
+ switch (memop) {
+ case MO_UB:
+ tmp32 = qemu_ld_ub;
+ break;
+ case MO_SB:
+ tmp32 = (int8_t)qemu_ld_ub;
+ break;
+ case MO_LEUW:
+ tmp32 = qemu_ld_leuw;
+ break;
+ case MO_LESW:
+ tmp32 = (int16_t)qemu_ld_leuw;
+ break;
+ case MO_LEUL:
+ tmp32 = qemu_ld_leul;
+ break;
+ case MO_BEUW:
+ tmp32 = qemu_ld_beuw;
+ break;
+ case MO_BESW:
+ tmp32 = (int16_t)qemu_ld_beuw;
+ break;
+ case MO_BEUL:
+ tmp32 = qemu_ld_beul;
+ break;
+ default:
+ tcg_abort();
+ }
+ tci_write_reg(t0, tmp32);
break;
- case INDEX_op_qemu_ld64:
+ case INDEX_op_qemu_ld_i64:
t0 = *tb_ptr++;
-#if TCG_TARGET_REG_BITS == 32
- t1 = *tb_ptr++;
-#endif
+ if (TCG_TARGET_REG_BITS == 32) {
+ t1 = *tb_ptr++;
+ }
taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- tmp64 = helper_ldq_mmu(env, taddr, tci_read_i(&tb_ptr));
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- tmp64 = tswap64(*(uint64_t *)(host_addr + GUEST_BASE));
-#endif
+ memop = tci_read_i(&tb_ptr);
+ switch (memop) {
+ case MO_UB:
+ tmp64 = qemu_ld_ub;
+ break;
+ case MO_SB:
+ tmp64 = (int8_t)qemu_ld_ub;
+ break;
+ case MO_LEUW:
+ tmp64 = qemu_ld_leuw;
+ break;
+ case MO_LESW:
+ tmp64 = (int16_t)qemu_ld_leuw;
+ break;
+ case MO_LEUL:
+ tmp64 = qemu_ld_leul;
+ break;
+ case MO_LESL:
+ tmp64 = (int32_t)qemu_ld_leul;
+ break;
+ case MO_LEQ:
+ tmp64 = qemu_ld_leq;
+ break;
+ case MO_BEUW:
+ tmp64 = qemu_ld_beuw;
+ break;
+ case MO_BESW:
+ tmp64 = (int16_t)qemu_ld_beuw;
+ break;
+ case MO_BEUL:
+ tmp64 = qemu_ld_beul;
+ break;
+ case MO_BESL:
+ tmp64 = (int32_t)qemu_ld_beul;
+ break;
+ case MO_BEQ:
+ tmp64 = qemu_ld_beq;
+ break;
+ default:
+ tcg_abort();
+ }
tci_write_reg(t0, tmp64);
-#if TCG_TARGET_REG_BITS == 32
- tci_write_reg(t1, tmp64 >> 32);
-#endif
- break;
- case INDEX_op_qemu_st8:
- t0 = tci_read_r8(&tb_ptr);
- taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- t2 = tci_read_i(&tb_ptr);
- helper_stb_mmu(env, taddr, t0, t2);
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- *(uint8_t *)(host_addr + GUEST_BASE) = t0;
-#endif
- break;
- case INDEX_op_qemu_st16:
- t0 = tci_read_r16(&tb_ptr);
- taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- t2 = tci_read_i(&tb_ptr);
- helper_stw_mmu(env, taddr, t0, t2);
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- *(uint16_t *)(host_addr + GUEST_BASE) = tswap16(t0);
-#endif
+ if (TCG_TARGET_REG_BITS == 32) {
+ tci_write_reg(t1, tmp64 >> 32);
+ }
break;
- case INDEX_op_qemu_st32:
- t0 = tci_read_r32(&tb_ptr);
+ case INDEX_op_qemu_st_i32:
+ t0 = tci_read_r(&tb_ptr);
taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- t2 = tci_read_i(&tb_ptr);
- helper_stl_mmu(env, taddr, t0, t2);
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- *(uint32_t *)(host_addr + GUEST_BASE) = tswap32(t0);
-#endif
+ memop = tci_read_i(&tb_ptr);
+ switch (memop) {
+ case MO_UB:
+ qemu_st_b(t0);
+ break;
+ case MO_LEUW:
+ qemu_st_lew(t0);
+ break;
+ case MO_LEUL:
+ qemu_st_lel(t0);
+ break;
+ case MO_BEUW:
+ qemu_st_bew(t0);
+ break;
+ case MO_BEUL:
+ qemu_st_bel(t0);
+ break;
+ default:
+ tcg_abort();
+ }
break;
- case INDEX_op_qemu_st64:
+ case INDEX_op_qemu_st_i64:
tmp64 = tci_read_r64(&tb_ptr);
taddr = tci_read_ulong(&tb_ptr);
-#ifdef CONFIG_SOFTMMU
- t2 = tci_read_i(&tb_ptr);
- helper_stq_mmu(env, taddr, tmp64, t2);
-#else
- host_addr = (tcg_target_ulong)taddr;
- assert(taddr == host_addr);
- *(uint64_t *)(host_addr + GUEST_BASE) = tswap64(tmp64);
-#endif
+ memop = tci_read_i(&tb_ptr);
+ switch (memop) {
+ case MO_UB:
+ qemu_st_b(tmp64);
+ break;
+ case MO_LEUW:
+ qemu_st_lew(tmp64);
+ break;
+ case MO_LEUL:
+ qemu_st_lel(tmp64);
+ break;
+ case MO_LEQ:
+ qemu_st_leq(tmp64);
+ break;
+ case MO_BEUW:
+ qemu_st_bew(tmp64);
+ break;
+ case MO_BEUL:
+ qemu_st_bel(tmp64);
+ break;
+ case MO_BEQ:
+ qemu_st_beq(tmp64);
+ break;
+ default:
+ tcg_abort();
+ }
break;
default:
TODO();
projects / mirror_qemu.git / blobdiff