#include "qemu/osdep.h"
#include <glib/gstdio.h>
-#include <sys/mman.h>
#include "contrib/ivshmem-server/ivshmem-server.h"
-#include "libqos/pci-pc.h"
+#include "libqos/libqos-pc.h"
+#include "libqos/libqos-spapr.h"
#include "libqtest.h"
#include "qemu-common.h"
}
typedef struct _IVState {
- QTestState *qtest;
- void *reg_base, *mem_base;
- QPCIBus *pcibus;
+ QOSState *qs;
+ QPCIBar reg_bar, mem_bar;
QPCIDevice *dev;
} IVState;
QTestState *qtest = global_qtest;
unsigned res;
- global_qtest = s->qtest;
- res = qpci_io_readl(s->dev, s->reg_base + reg);
+ global_qtest = s->qs->qts;
+ res = qpci_io_readl(s->dev, s->reg_bar, reg);
g_test_message("*%s -> %x\n", name, res);
global_qtest = qtest;
const char *name = reg2str(reg);
QTestState *qtest = global_qtest;
- global_qtest = s->qtest;
+ global_qtest = s->qs->qts;
g_test_message("%x -> *%s\n", v, name);
- qpci_io_writel(s->dev, s->reg_base + reg, v);
+ qpci_io_writel(s->dev, s->reg_bar, reg, v);
+ global_qtest = qtest;
+}
+
+static inline void read_mem(IVState *s, uint64_t off, void *buf, size_t len)
+{
+ QTestState *qtest = global_qtest;
+
+ global_qtest = s->qs->qts;
+ qpci_memread(s->dev, s->mem_bar, off, buf, len);
+ global_qtest = qtest;
+}
+
+static inline void write_mem(IVState *s, uint64_t off,
+ const void *buf, size_t len)
+{
+ QTestState *qtest = global_qtest;
+
+ global_qtest = s->qs->qts;
+ qpci_memwrite(s->dev, s->mem_bar, off, buf, len);
global_qtest = qtest;
}
static void cleanup_vm(IVState *s)
{
g_free(s->dev);
- qpci_free_pc(s->pcibus);
- qtest_quit(s->qtest);
+ qtest_shutdown(s->qs);
}
static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)
{
uint64_t barsize;
+ const char *arch = qtest_get_arch();
- s->qtest = qtest_start(cmd);
- s->pcibus = qpci_init_pc();
- s->dev = get_device(s->pcibus);
+ if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
+ s->qs = qtest_pc_boot(cmd);
+ } else if (strcmp(arch, "ppc64") == 0) {
+ s->qs = qtest_spapr_boot(cmd);
+ } else {
+ g_printerr("ivshmem-test tests are only available on x86 or ppc64\n");
+ exit(EXIT_FAILURE);
+ }
+ s->dev = get_device(s->qs->pcibus);
- s->reg_base = qpci_iomap(s->dev, 0, &barsize);
- g_assert_nonnull(s->reg_base);
+ s->reg_bar = qpci_iomap(s->dev, 0, &barsize);
g_assert_cmpuint(barsize, ==, 256);
if (msix) {
qpci_msix_enable(s->dev);
}
- s->mem_base = qpci_iomap(s->dev, 2, &barsize);
- g_assert_nonnull(s->mem_base);
+ s->mem_bar = qpci_iomap(s->dev, 2, &barsize);
g_assert_cmpuint(barsize, ==, TMPSHMSIZE);
qpci_device_enable(s->dev);
for (i = 0; i < G_N_ELEMENTS(data); i++) {
data[i] = i;
}
- qtest_memwrite(s->qtest, (uintptr_t)s->mem_base, data, sizeof(data));
+ write_mem(s, 0, data, sizeof(data));
/* verify write */
for (i = 0; i < G_N_ELEMENTS(data); i++) {
/* read it back and verify read */
memset(data, 0, sizeof(data));
- qtest_memread(s->qtest, (uintptr_t)s->mem_base, data, sizeof(data));
+ read_mem(s, 0, data, sizeof(data));
for (i = 0; i < G_N_ELEMENTS(data); i++) {
g_assert_cmpuint(data[i], ==, i);
}
/* host write, guest 1 & 2 read */
memset(tmpshmem, 0x42, TMPSHMSIZE);
- qtest_memread(s1->qtest, (uintptr_t)s1->mem_base, data, TMPSHMSIZE);
+ read_mem(s1, 0, data, TMPSHMSIZE);
for (i = 0; i < TMPSHMSIZE; i++) {
g_assert_cmpuint(data[i], ==, 0x42);
}
- qtest_memread(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
+ read_mem(s2, 0, data, TMPSHMSIZE);
for (i = 0; i < TMPSHMSIZE; i++) {
g_assert_cmpuint(data[i], ==, 0x42);
}
/* guest 1 write, guest 2 read */
memset(data, 0x43, TMPSHMSIZE);
- qtest_memwrite(s1->qtest, (uintptr_t)s1->mem_base, data, TMPSHMSIZE);
+ write_mem(s1, 0, data, TMPSHMSIZE);
memset(data, 0, TMPSHMSIZE);
- qtest_memread(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
+ read_mem(s2, 0, data, TMPSHMSIZE);
for (i = 0; i < TMPSHMSIZE; i++) {
g_assert_cmpuint(data[i], ==, 0x43);
}
/* guest 2 write, guest 1 read */
memset(data, 0x44, TMPSHMSIZE);
- qtest_memwrite(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
+ write_mem(s2, 0, data, TMPSHMSIZE);
memset(data, 0, TMPSHMSIZE);
- qtest_memread(s1->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
+ read_mem(s1, 0, data, TMPSHMSIZE);
for (i = 0; i < TMPSHMSIZE; i++) {
g_assert_cmpuint(data[i], ==, 0x44);
}
g_assert_cmpint(vm1, !=, vm2);
/* check number of MSI-X vectors */
- global_qtest = s1->qtest;
+ global_qtest = s1->qs->qts;
if (msi) {
ret = qpci_msix_table_size(s1->dev);
g_assert_cmpuint(ret, ==, nvectors);
g_assert_cmpuint(ret, !=, 0);
/* ping vm1 -> vm2 on vector 1 */
- global_qtest = s2->qtest;
+ global_qtest = s2->qs->qts;
if (msi) {
ret = qpci_msix_pending(s2->dev, 1);
g_assert_cmpuint(ret, ==, 0);
static void test_ivshmem_hotplug(void)
{
+ const char *arch = qtest_get_arch();
gchar *opts;
qtest_start("");
opts = g_strdup_printf("'shm': '%s', 'size': '1M'", tmpshm);
qpci_plug_device_test("ivshmem", "iv1", PCI_SLOT_HP, opts);
- qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP);
+ if (strcmp(arch, "ppc64") != 0) {
+ qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP);
+ }
qtest_end();
g_free(opts);
int main(int argc, char **argv)
{
int ret, fd;
+ const char *arch = qtest_get_arch();
gchar dir[] = "/tmp/ivshmem-test.XXXXXX";
#if !GLIB_CHECK_VERSION(2, 31, 0)
qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev);
if (g_test_slow()) {
qtest_add_func("/ivshmem/pair", test_ivshmem_pair);
- qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi);
- qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq);
+ if (strcmp(arch, "ppc64") != 0) {
+ qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi);
+ qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq);
+ }
}
ret = g_test_run();