[
{,
- "EventCode": "0x0",
- "EventName": "PM_SUSPENDED",
- "BriefDescription": "Counter OFF",
- "PublicDescription": ""
+ "EventCode": "0x20036",
+ "EventName": "PM_BR_2PATH",
+ "BriefDescription": "Branches that are not strongly biased"
},
{,
- "EventCode": "0x10026",
- "EventName": "PM_TABLEWALK_CYC",
- "BriefDescription": "Cycles when an instruction tablewalk is active",
- "PublicDescription": ""
+ "EventCode": "0x40036",
+ "EventName": "PM_BR_2PATH",
+ "BriefDescription": "Branches that are not strongly biased"
},
{,
- "EventCode": "0x1E04C",
- "EventName": "PM_DPTEG_FROM_LL4",
- "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
- "PublicDescription": ""
+ "EventCode": "0x40056",
+ "EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
+ "BriefDescription": "Local memory above threshold for LSU medium"
},
{,
- "EventCode": "0x1F14E",
- "EventName": "PM_MRK_DPTEG_FROM_L2MISS",
- "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
- "PublicDescription": ""
+ "EventCode": "0x2C056",
+ "EventName": "PM_DTLB_MISS_4K",
+ "BriefDescription": "Data TLB Miss page size 4k"
},
{,
- "EventCode": "0x10060",
- "EventName": "PM_TM_TRANS_RUN_CYC",
- "BriefDescription": "run cycles in transactional state",
- "PublicDescription": ""
+ "EventCode": "0x40118",
+ "EventName": "PM_MRK_DCACHE_RELOAD_INTV",
+ "BriefDescription": "Combined Intervention event"
},
{,
- "EventCode": "0x2C012",
- "EventName": "PM_CMPLU_STALL_DCACHE_MISS",
- "BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest",
- "PublicDescription": ""
+ "EventCode": "0x4F148",
+ "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
+ "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
- "EventCode": "0x2E04C",
- "EventName": "PM_DPTEG_FROM_MEMORY",
- "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
- "PublicDescription": ""
+ "EventCode": "0x301E8",
+ "EventName": "PM_THRESH_EXC_64",
+ "BriefDescription": "Threshold counter exceeded a value of 64"
},
{,
- "EventCode": "0x2C056",
- "EventName": "PM_DTLB_MISS_4K",
- "BriefDescription": "Data TLB Miss page size 4k",
- "PublicDescription": ""
+ "EventCode": "0x4E04E",
+ "EventName": "PM_DPTEG_FROM_L3MISS",
+ "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
- "EventCode": "0x3000C",
- "EventName": "PM_FREQ_DOWN",
- "BriefDescription": "Power Management: Below Threshold B",
- "PublicDescription": ""
+ "EventCode": "0x40050",
+ "EventName": "PM_SYS_PUMP_MPRED_RTY",
+ "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
- "EventCode": "0x3D142",
- "EventName": "PM_MRK_DATA_FROM_LMEM",
- "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
- "PublicDescription": ""
+ "EventCode": "0x1F14E",
+ "EventName": "PM_MRK_DPTEG_FROM_L2MISS",
+ "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
- "EventCode": "0x3F142",
- "EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
- "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
- "PublicDescription": ""
+ "EventCode": "0x4D018",
+ "EventName": "PM_CMPLU_STALL_BRU",
+ "BriefDescription": "Completion stall due to a Branch Unit"
},
{,
- "EventCode": "0x301E8",
- "EventName": "PM_THRESH_EXC_64",
- "BriefDescription": "Threshold counter exceeded a value of 64",
- "PublicDescription": ""
+ "EventCode": "0x45052",
+ "EventName": "PM_4FLOP_CMPL",
+ "BriefDescription": "4 FLOP instruction completed"
},
{,
- "EventCode": "0x40118",
- "EventName": "PM_MRK_DCACHE_RELOAD_INTV",
- "BriefDescription": "Combined Intervention event",
- "PublicDescription": ""
+ "EventCode": "0x3D142",
+ "EventName": "PM_MRK_DATA_FROM_LMEM",
+ "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load"
},
{,
"EventCode": "0x4C01E",
"EventName": "PM_CMPLU_STALL_CRYPTO",
- "BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish",
- "PublicDescription": ""
+ "BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish"
},
{,
- "EventCode": "0x4D018",
- "EventName": "PM_CMPLU_STALL_BRU",
- "BriefDescription": "Completion stall due to a Branch Unit",
- "PublicDescription": ""
+ "EventCode": "0x3000C",
+ "EventName": "PM_FREQ_DOWN",
+ "BriefDescription": "Power Management: Below Threshold B"
},
{,
"EventCode": "0x4D128",
"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
- "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load",
- "PublicDescription": ""
+ "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load"
},
{,
- "EventCode": "0x4E04E",
- "EventName": "PM_DPTEG_FROM_L3MISS",
- "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
- "PublicDescription": ""
+ "EventCode": "0x4D054",
+ "EventName": "PM_8FLOP_CMPL",
+ "BriefDescription": "8 FLOP instruction completed"
},
{,
- "EventCode": "0x4F142",
- "EventName": "PM_MRK_DPTEG_FROM_L3",
- "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
- "PublicDescription": ""
+ "EventCode": "0x10026",
+ "EventName": "PM_TABLEWALK_CYC",
+ "BriefDescription": "Cycles when an instruction tablewalk is active"
},
{,
- "EventCode": "0x4F148",
- "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
- "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
- "PublicDescription": ""
+ "EventCode": "0x2C012",
+ "EventName": "PM_CMPLU_STALL_DCACHE_MISS",
+ "BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest"
},
{,
- "EventCode": "0x40050",
- "EventName": "PM_SYS_PUMP_MPRED_RTY",
- "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
- "PublicDescription": ""
+ "EventCode": "0x2E04C",
+ "EventName": "PM_DPTEG_FROM_MEMORY",
+ "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
- "EventCode": "0x40056",
- "EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
- "BriefDescription": "Local memory above threshold for LSU medium",
- "PublicDescription": ""
+ "EventCode": "0x3F142",
+ "EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
+ "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
- "EventCode": "0x4D054",
- "EventName": "PM_8FLOP_CMPL",
- "BriefDescription": "8 FLOP instruction completed",
- "PublicDescription": ""
+ "EventCode": "0x4F142",
+ "EventName": "PM_MRK_DPTEG_FROM_L3",
+ "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
- "EventCode": "0x45050",
- "EventName": "PM_1FLOP_CMPL",
- "BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed",
- "PublicDescription": ""
+ "EventCode": "0x10060",
+ "EventName": "PM_TM_TRANS_RUN_CYC",
+ "BriefDescription": "run cycles in transactional state"
},
{,
- "EventCode": "0x45052",
- "EventName": "PM_4FLOP_CMPL",
- "BriefDescription": "4 FLOP instruction completed",
- "PublicDescription": ""
+ "EventCode": "0x1E04C",
+ "EventName": "PM_DPTEG_FROM_LL4",
+ "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
+ },
+ {,
+ "EventCode": "0x45050",
+ "EventName": "PM_1FLOP_CMPL",
+ "BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed"
}
-]
+]
\ No newline at end of file
projects / mirror_ubuntu-artful-kernel.git / blobdiff