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disas/mips: fix disassembling R6 instructions
authorYongbok Kim <yongbok.kim@imgtec.com>
Tue, 30 Jun 2015 15:33:15 +0000 (16:33 +0100)
committerLeon Alrae <leon.alrae@imgtec.com>
Wed, 15 Jul 2015 13:07:20 +0000 (14:07 +0100)
commit6b9c26fb5eed2345398daca4eef601da2f3d7867
tree285285860c7d2e441592aea59bc9f777d9b514b4tree
parentd4f4f0d5d9e74c19614479592c8bc865d92773d0commit | diff
disas/mips: fix disassembling R6 instructions

In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF
and CACHE instructions have 9 bits offsets.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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