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atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patch
authorHuang, Xiong <xiong@qca.qualcomm.com>
Wed, 18 Apr 2012 22:01:27 +0000 (22:01 +0000)
committerDavid S. Miller <davem@davemloft.net>
Fri, 20 Apr 2012 00:14:20 +0000 (20:14 -0400)
commit5cbdcc2f49b4a8372052952799d2cb1de387443b
tree7a6ad570c04d880a26febdc1ad613e8a3a9a90detree
parent7f5544d6693ab2593b4f13521a577387f3be6b2fcommit | diff
atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patch

bit MASTER_CTRL_CLK_SEL_DIS could be set before enter suspend
clear it after resume to enable pclk(PCIE clock) switch to
low frequency(25M) in some circumstances to save power.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/atheros/atl1c/atl1c_main.c diff | blob | blame | history
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