]> git.proxmox.com Git - mirror_qemu.git/commit - hw/intc/riscv_aclint.c
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
authorAnup Patel <anup.patel@wdc.com>
Tue, 31 Aug 2021 11:06:01 +0000 (16:36 +0530)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Sep 2021 21:56:49 +0000 (07:56 +1000)
commitb8fb878aa2485fd41502295f0ff5362a67c8ba68
tree42250dd651e676117144343ea1d353a1d8ceb6e9
parentcc63a18282d8e8cd96d8bf26c29cad2e879ff9f6
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

The RISC-V ACLINT is more modular and backward compatible with
original SiFive CLINT so instead of duplicating the original
SiFive CLINT implementation we upgrade the current SiFive CLINT
implementation to RISC-V ACLINT implementation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210831110603.338681-3-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/intc/riscv_aclint.c
hw/riscv/microchip_pfsoc.c
hw/riscv/shakti_c.c
hw/riscv/sifive_e.c
hw/riscv/sifive_u.c
hw/riscv/spike.c
hw/riscv/virt.c
include/hw/intc/riscv_aclint.h