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hw/misc: Add a model of the Xilinx Versal CRL
authorEdgar E. Iglesias <edgar.iglesias@amd.com>
Wed, 6 Apr 2022 17:43:02 +0000 (18:43 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 21 Apr 2022 10:37:03 +0000 (11:37 +0100)
commit369e5cb0c948b65e0845ca3394e25d757dd93206
treed5f0ebf016671a733ddc87b4717f6a342f7998f4tree
parent67a645a35110f300144ae844cbf839762abcd98dcommit | diff
hw/misc: Add a model of the Xilinx Versal CRL

Add a model of the Xilinx Versal CRL.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/misc/meson.build diff | blob | blame | history
hw/misc/xlnx-versal-crl.c [new file with mode: 0644] blob
include/hw/misc/xlnx-versal-crl.h [new file with mode: 0644] blob
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