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RISC-V HART Array
authorMichael Clark <mjc@sifive.com>
Fri, 2 Mar 2018 12:31:12 +0000 (01:31 +1300)
committerMichael Clark <mjc@sifive.com>
Tue, 6 Mar 2018 19:30:28 +0000 (08:30 +1300)
commit4b50b8d9f2bdc007d632a6d0781de1126c5d9c76
treeebe0a821d00d0f1a0133438ea0f1adac8e2160f7tree
parent5033606780b9743921de95adb295bf1a03135d2ccommit | diff
RISC-V HART Array

Holds the state of a heterogenous array of RISC-V hardware threads.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
hw/riscv/riscv_hart.c [new file with mode: 0644] blob
include/hw/riscv/riscv_hart.h [new file with mode: 0644] blob
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