]> git.proxmox.com Git - mirror_qemu.git/commit - include/hw/riscv/spike.h
RISC-V Spike Machines
authorMichael Clark <mjc@sifive.com>
Fri, 2 Mar 2018 12:31:13 +0000 (01:31 +1300)
committerMichael Clark <mjc@sifive.com>
Tue, 6 Mar 2018 19:30:28 +0000 (08:30 +1300)
commit5b4beba1246ff163415bde41cd76935012b16823
treeac3596e00957f860fefdfdf2503aff64ef229f74
parent1e24429e40df81270012538851c75e30c53eec21
RISC-V Spike Machines

RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V
Instruction Set Simulator. The following machines are implemented:

- 'spike_v1.9.1'; HTIF console, config-string, Privileged ISA Version 1.9.1
- 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
hw/riscv/spike.c [new file with mode: 0644]
include/hw/riscv/spike.h [new file with mode: 0644]