]> git.proxmox.com Git - mirror_qemu.git/commit - target/arm/helper.c
target/arm: Make CCR register banked for v8M
authorPeter Maydell <peter.maydell@linaro.org>
Thu, 7 Sep 2017 12:54:54 +0000 (13:54 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 7 Sep 2017 12:54:54 +0000 (13:54 +0100)
commit9d40cd8a68cfc7606f4548cc9e812bab15c6dc28
tree5ea2b0c184445a132503a6ae8b8710be0e709fac
parentecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9
target/arm: Make CCR register banked for v8M

Make the CCR register banked if v8M security extensions are enabled.

This is slightly more complicated than the other "add banking"
patches because there is one bit in the register which is not
banked. We keep the live data in the NS copy of the register,
and adjust it on register reads and writes. (Since we don't
currently implement the behaviour that the bit controls, there
is nowhere else that needs to care.)

This patch includes the enforcement of the bits which are newly
RES1 in ARMv8M.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1503414539-28762-17-git-send-email-peter.maydell@linaro.org
hw/intc/armv7m_nvic.c
target/arm/cpu.c
target/arm/cpu.h
target/arm/helper.c
target/arm/machine.c